Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)

Abstract

Hyperdimensional (HD) computing is a brain-inspired computation model capable of learning from only a few examples. It uses random binary vectors with high dimensionality. We present device-architecture co-design, leveraging 3D vertical resistive switching random access memory (3D VRRAM), for HD computing targeting language recognition applications. Multiplication-addition-permutation (MAP), the essential operations of HD computing, are experimentally demonstrated using 4-layer 3D VRRAMs/FinFETs, with extensive cycle-to-cycle (up to 1012 cycles) and device-to-device (256 RRAM cells) measurements. At the 28-nm node, the resulting 3D in-memory architecture is projected to achieve two orders of magnitude area reduction over a digital CMOS design, and exhibit strong resilience to hard errors induced by RRAM endurance failures. This makes a promising case for using various types of RRAM (>1k endurance) for memory-centric HD cognitive systems.