Endcap Region Research Articles

The New Small Wheel Trigger for the ATLAS experiment

The ATLAS New Small Wheel (NSW) Muon spectrometer upgrade, completed in 2022, was the largest Phase I detector upgrade among LHC experiments. The NSW enhances triggering in the endcap region (1.3<|η|<2.4) by confirming muons from the Interaction Point (IP) and rejecting fake contributions. It also improves muon tracking with 2.5 million high-resolution channels across 16 layers. The NSW Trigger, based on small-strip Thin Gap Chambers (sTGC) and Micromegas (MM) technologies, provides Level-1 triggers at every Bunch Crossing (BC) with a fixed low latency (44 BC). Integrated into ATLAS in 2023, the NSW Trigger significantly reduces fake rates and overall readout deadtime. The custom electronics of the NSW Trigger system efficiently collect, process, and trigger on IP muons, focusing on the fully operational sTGC pad-only path based on the Pad Trigger (PT) and Trigger Processor (TP) FPGA based boards. Performance studies using 13.6TeV pp collisions are presented, demonstrating NSW’s readiness for the High Luminocity LHC (HL-LHC) era and outlining Phase II upgrade perspectives.

Low gain avalanche detectors for precision timing in the CMS MTD endcap timing layer

The MIP Timing Detector (MTD) of the Compact Muon Solenoid (CMS) is designed to provide precision timing information (with resolution of ∼40 ps per layer) for charged particles, with hermetic coverage up to a pseudo-rapidity of |η| = 3. This upgrade will reduce the effects of pile-up expected under the High-Luminosity LHC running conditions and brings new and unique capabilities to the CMS detector. The time information assigned to each track will enable the use of 4D reconstruction algorithms and will further discriminate in the time domain interaction vertices within the same bunch crossing to recover the track purity of vertices in current LHC conditions. The endcap region of the MTD, called the Endcap Timing Layer (ETL) will be instrumented with silicon-based low gain avalanche detectors (LGADs), covering the high radiation pseudo-rapidity region between |η| = 1.6 and 3.0. Each endcap will be instrumented with a two-disk system of LGADs, read out by Endcap Timing Readout Chips (ETROCs), being designed for precision timing measurements. We will present an overview of the MTD ETL design, which is detailed in the MTD technical design report. We will also present the R&D and test beam studies that were instrumental for achieving the ETL design, characterization of the LGAD sensors, as well as recent progress on the development of the ETROC readout electronics.

The ATLAS experiment at the CERN Large Hadron Collider: a description of the detector configuration for Run 3

The ATLAS detector is installed in its experimental cavern at Point 1 of the CERN Large Hadron Collider. During Run 2 of the LHC, a luminosity of ℒ = 2 × 1034 cm-2 s-1 was routinely achieved at the start of fills, twice the design luminosity. For Run 3, accelerator improvements, notably luminosity levelling, allow sustained running at an instantaneous luminosity of ℒ = 2 × 1034 cm-2 s-1, with an average of up to 60 interactions per bunch crossing. The ATLAS detector has been upgraded to recover Run 1 single-lepton trigger thresholds while operating comfortably under Run 3 sustained pileup conditions. A fourth pixel layer 3.3 cm from the beam axis was added before Run 2 to improve vertex reconstruction and b-tagging performance. New Liquid Argon Calorimeter digital trigger electronics, with corresponding upgrades to the Trigger and Data Acquisition system, take advantage of a factor of 10 finer granularity to improve triggering on electrons, photons, taus, and hadronic signatures through increased pileup rejection. The inner muon endcap wheels were replaced by New Small Wheels with Micromegas and small-strip Thin Gap Chamber detectors, providing both precision tracking and Level-1 Muon trigger functionality. Trigger coverage of the inner barrel muon layer near one endcap region was augmented with modules integrating new thin-gap resistive plate chambers and smaller-diameter drift-tube chambers. Tile Calorimeter scintillation counters were added to improve electron energy resolution and background rejection. Upgrades to Minimum Bias Trigger Scintillators and Forward Detectors improve luminosity monitoring and enable total proton-proton cross section, diffractive physics, and heavy ion measurements. These upgrades are all compatible with operation in the much harsher environment anticipated after the High-Luminosity upgrade of the LHC and are the first steps towards preparing ATLAS for the High-Luminosity upgrade of the LHC. This paper describes the Run 3 configuration of the ATLAS detector.

Operation and performance of the Belle II Aerogel RICH detector

The Belle II experiment at the SuperKEKB asymmetric-energy e+e− collider is a B factory experiment to search for new phenomena beyond the Standard Model. One of the most important keys in the experiment is particle identification, in particular the separation between kaons and pions. Therefore, a proximity focusing Aerogel Ring Imaging Cherenkov (ARICH) counter is used in the forward endcap region to distinguish kaons and pions with momenta up to 4 GeV/c. The ARICH counter consists of a silica aerogel radiator and Hybrid Avalanche Photo Detectors (HAPDs). When a charged particle passes through the radiator, Cherenkov photons are emitted and then detected by the HAPDs.The Belle II experiment started its physics run in 2019 and collected 424 fb−1 of collision data. The ARICH counter is running stably and the performance is in line with our expectations. We report the details of the operation of the HAPDs and the readout electronics. We also report on the performance of the ARICH counter based on the data.

Study of discharges in the CMS GEM GE1/1 station with LHC beam

The Large Hadron Collider (LHC) and the experiments installed there are being upgraded for the High Luminosity LHC project that will provide a greatly enlarged data sample in the search for physics beyond the Standard Model. During Long Shutdown 2, from 2018 to the first months of 2022, some of these upgrades were completed. In particular, the muon spectrometer of the CMS experiment was upgraded with installation of the GE1/1 detector station, based on Gas Electron Multiplier (GEM) technology. This station is positioned in the endcap region of the CMS muon system and covers the pseudorapidity range 1.55 < |η| < 2.18. On the 5th of July, 2022, Run 3 of the LHC began with collision energy of 13.6 TeV. The newly installed GEM detectors experienced high-voltage discharges when the beams were colliding inside CMS. To monitor these events and to understand how to safely operate the detectors, a study of these phenomena became necessary. The intensity of discharge current and the discharge rate were recorded in different detectors as a function of luminosity and time. It was observed that some chambers have a significantly higher discharge rate than the modal value of rate over the entire chamber population. The reasons responsible for this behavior are currently under investigation. In this contribution, an analysis of discharges will be presented, illustrating the dependence of discharge rate on different LHC beam configurations and the high voltage working point of the chambers.

A 40 MHz Level-1 trigger scouting system for the CMS Phase-2 upgrade

The CMS Phase-2 upgrade for the HL-LHC aims at preserving and expanding the current physics capability of the experiment under extreme pileup conditions. A new tracking system incorporates a track finder processor, providing tracks to the Level-1 (L1) trigger. A new high-granularity calorimeter provides fine-grained energy deposition information in the endcap region. New front-end and back-end electronics feed the L1 trigger with high-resolution information from the barrel calorimeter and the muon systems. The upgraded L1 will be based primarily on the Xilinx Ultrascale Plus series of FPGAs, capable of sophisticated feature searches with resolution often similar to the offline reconstruction. The L1 Data Scouting system (L1DS) will capture L1 intermediate data produced by the trigger processors at the beam-crossing rate of 40 MHz, and carry out online analyses based on these limited-resolution data. The L1DS will provide fast and virtually unlimited statistics for detector diagnostics, alternative luminosity measurements, and, in some cases, calibrations. It also has the potential to enable the study of otherwise inaccessible signatures, either too common to fit in the L1 trigger accept budget or with requirements that are orthogonal to “mainstream” physics. The requirements and architecture of the L1DS system are presented, as well as some of the potential physics opportunities under study. The first results from the assembly and commissioning of a demonstrator currently being installed for LHC Run-3 are also presented. The demonstrator collects data from the Global Muon Trigger, the Layer-2 Calorimeter Trigger, the Barrel Muon Track Finder, and the Global Trigger systems of the current CMS L1. This demonstrator, as a data acquisition (DAQ) system operating at the LHC bunch-crossing rate, faces many of the challenges of the Phase-2 system, albeit with scaled-down connectivity, reduced data throughput and physics capabilities, providing a testing ground for new techniques of online data reduction and processing.

Sector logic development for the ATLAS Level-0 muon trigger at HL-LHC

The design of the Sector Logic (SL) for the ATLAS Level-0 muon trigger at the HL-LHC and the milestones achieved on the hardware and firmware developments are presented. The SL board includes an XCVU13P FPGA, FireFly transceivers, an IPMC mezzanine card developed by CERN, and a Mercury XU5 MPSoC mezzanine card. The first prototype of the SL board was produced, and all its functions have been verified. Fast tracking using Thin-Gap Chamber (TGC) hits, a core part of the Level-0 muon trigger for the endcap regions, has been developed for the full TGC detector coverage and the performance was confirmed with post-synthesis simulations. The processing of the TGC hits from ∼7000 channels has been demonstrated with a XCVU13P FPGA within ∼100 ns.

System-level performance study and commissioning of TGC front-end electronics for Phase-2 upgrade of LHC-ATLAS

The Thin Gap Chamber (TGC) of the ATLAS experiment at the LHC are responsible to provide muons trigger segments in the endcap region at the hardware trigger stage. The front-end electronics system of the TGC will be upgraded for the HL-LHC to send binary hit-map at every bunch crossing (BC) to the back-end system. Such an operation poses lots of unique challenges: hit BC identification with high efficiency, fine-tuned clock distribution, robustness for SEU, and capability of timing calibration. Accommodating these requirements, the primary processor board (PS Board) is in charge of data processing and reception of control signals from the back-end. An independent control module (JATHub) will take responsibility for FPGA configuration and clock phase monitoring of the PS Boards with an SoC-based design. Prototyping and system-level demonstration with the prototypes have been performed. This experience validates our operation and commissioning strategy of the TGC electronics system for the HL-LHC.

Certification of a new generation of Resistive Plate Chambers for the Phase-1 BIS78 upgrade of the ATLAS Muon Spectrometer

In preparation for the coming years of LHC running at higher luminosity, two upgrade projects of the ATLAS Muon Spectrometer have been developed: the New Small Wheel project, improving the trigger in the end-cap regions, and the BIS78 project, dedicated to the transition region between the barrel and the endcaps (1< |η| <1.3). The BIS78 project will add 32 RPC triplets on the edges of the inner barrel sectors where the ATLAS toroid is present. These new generation of RPCs are characterized by thinner gas gaps (1 mm vs 2 mm of the legacy RPCs) as well as thinner resistive electrodes, together with a new high gain front-end electronics operating at lower voltage. Sixteen BIS78 stations have been already installed in the ATLAS Muon spectrometer between 2020 and 2021 and are being commissioned during this year. The status of the project, the status of the commissioning as well as the overall performances of the installed RPCs will be presented.

The PANDA EDD prototype in Giessen Cosmic Station

The PANDA detector at the future Facility for Antiproton and Ion Research (FAIR) is currently being constructed in Darmstadt, Germany. It contains a fixed proton target and an antiproton beam with a momentum range between 1.5 GeV/c to 15 GeV/c. Two Cherenkov detectors are used to identify charged hadrons. The Disc DIRC (EDD) covers polar angles between 5° to 22° in the endcap region. In order to test the performance of the EDD prototype, the experimental setup driven by cosmic muons was built at the JLU in Giessen. It is called the Giessen Cosmic Station (GCS) and contains four tracking boxes for tracking muons, two trigger plates, and a lead absorber. The prototype of the EDD detector is integrated to the GCS setup to reconstruct the Cherenkov angle of each muon tracked by the GCS hodoscope.This work covers the technical design of the GCS and the performance tests of the EDD prototype in the GCS.

The New Small Wheel High Voltage Infrastructure

The ATLAS Muon Spectrometer is subjected to a series of upgrades in order to face the High Luminosity era of Phase-II. One of the main projects is the New Small Wheel (NSW), which has replaced the existing Small Wheel (SW), and is a perfect complement to the ATLAS Muon Spectrometer (MS) in the Endcap regions. The NSW is the combination of two prototype detector technologies, the small Thin Gap Chambers (sTGC) and the resistive Micromegas (MM). In order to operate smoothly the two technologies, a dedicated hardware infrastructure has been installed and modified accordingly based on the needs of each muon sub-system. In order to control and monitor the hardware for both technologies a Detector Control System (DCS) has been developed, following the architecture of the legacy Muon sub-systems. Aim of this work is the presentation of the development and implementation of these HV DCS systems under the Point 1 schema.

L1 Triggering on High-Granularity Information at the HL-LHC

The CMS collaboration is building a high-granularity calorimeter (HGCAL) for the endcap regions as part of its planned upgrade for the High-Luminosity LHC. The calorimetric data will form part of the Level-1 trigger (hardware) of the CMS experiment, reducing the event rate from the nominal 40 MHz to 750 kHz with a decision time (latency) of 12.5 microseconds. In addition to basic tracking information, which will also be available in the Level-1 trigger system, the use of particle-flow techniques will be facilitated as part of the trigger system. Around 1-million “trigger channels” are read at 40 MHz from the HGCAL, presenting a significant challenge in terms of data manipulation and processing for the trigger system: the trigger data volumes will be an order of magnitude above those currently handled at CMS. In addition, the high luminosity will result in an average of 140 (or more) interactions per bunch crossing that produce a huge background rate in the forward region and these will need to be efficiently rejected by the trigger algorithms. Furthermore, the reconstruction of particle clusters used for particle flow in high hit-rate events presents a complex computational problem associated with the trigger. We present the status of the trigger architecture and design, as well as the algorithmic concepts needed in order to tackle these major issues.

CMS improved resistive plate chamber studies in preparation for the high luminosity phase of the LHC

The high luminosity expected from the HL-LHC will provide a great opportunity for precise physics measurements and searches for new physics. Nevertheless, the increased rate of particles coming from the collisions will pose a challenge for the CMS detectors. To prepare the muon system for the challenging conditions during the high luminosity phase, several upgrades have been planned and are being developed. Thanks to their fast time and space resolution, resistive plate chambers form part of the trigger system and are installed both in the barrel and endcap regions as a subsystem of the muon detector. As part of the upgrades, the muon forward region will be enhanced with two stations, called RE3/1 and RE4/1, equipped with improved Resistive Plate Chambers (iRPCs). These detectors use thinner electrodes, a narrower gas gap (1.4 mm compared to 2 mm in the current design) and improved front-end electronics. These features allow them to withstand particle rates up to a few kHz/cm2. Furthermore, they will extend the geometrical acceptance of the RPCs from a pseudorapidity of 1.9 to 2.4. In this work we present different studies related to the iRPC prototypes in preparation for the high luminosity phase of the LHC.

A High-Granularity Timing Detector for the ATLAS Phase-II upgrade

The increase of the particle flux at the HL-LHC with instantaneous luminosities up to L=7.5 × 10 34 cm −2 s −1 will have a severe impact on the ATLAS detector reconstruction and trigger performance. The end-cap and forward region where the liquid Argon calorimeter has coarser granularity and the inner tracker has poorer momentum resolution will be particularly affected. A High Granularity Timing Detector will be installed in front of the liquid Argon end-cap calorimeters to help in charged-particle reconstruction and luminosity measurement. This low angle detector is introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0. Two silicon-sensor double-sided per end-cap will provide precision timing information for minimum-ionizing particles with a resolution as good as 30 ps per track in order to assign each particle to the correct vertex. Readout cells have a size of 1.3 mm × 1.3 mm, leading to a highly granular detector with 3.7 million channels. The Low Gain Avalanche Detectors technology has been chosen as sensor as it provides excellent timing performance. The requirements and overall specifications of the High Granularity Timing Detector are presented as well as the technical design and the project status. The on-going R&D effort carried out to study the sensors, the readout ASIC, and the other components, supported by laboratory and test beam results, are also presented.

The CMS MTD Endcap Timing Layer: Precision timing with Low Gain Avalanche Diodes

The MIP Timing Detector of the CMS detector will provide precision timestamps with 40 ps resolution for all charged particles up to a pseudorapidity of η=3.0. This upgrade will mitigate the effects of pile-up expected under the High-Luminosity LHC running conditions and bring new and unique capabilities to the CMS detector. The endcap region of the MIP Timing Detector, called the Endcap Timing Layer, will be instrumented with silicon Low-Gain Avalanche Diodes, covering the high-radiation pseudorapidity region 1.6<η<3.0. The LGAD sensors will be read out by the ETROC readout chip, which is being designed for precision timing measurements. We present recent progress in the characterization of LGAD sensors for the Endcap Timing Layer and the development of ETROC, including test beam and bench measurements.

Design and testing of an sTGC ASIC interface board for the ATLAS New Small Wheel upgrade

The ATLAS experiment will replace the present small wheel (SW) detector with a new small wheel detector (NSW) aiming to improve the performance of muon triggering and precision tracking in the endcap region at the high-luminosity LHC. small-strip thin gap chamber (sTGC) is one of the two new detector technologies used in this upgrade. A few custom-designed ASICs are needed for the sTGC detector. An sTGC ASIC interface board is designed to test ASIC-to-ASIC communication and to validate the functionality of the entire system. A test platform with the final readout system is set up and the whole sTGC readout chain is demonstrated for the first time. Key parameters in the readout chain are discussed and the results are shown.

A program to drive the ATLAS Local Trigger Interface (ALTI) at the ATLAS experiment

During the High Luminosity upgrade of the Large Hadron Collider at CERN, the LHC experiments will undergo a series of upgrades in order to maintain high physics performance following an increased data rate. The largest Phase 1 upgrade project at the ATLAS muon system is the replacement of the current inner station (end-cap regions) with the New Small Wheels. In addition, the ATLAS Local Trigger Interface (ALTI), a part of the Timing, Trigger and Control (TTC) system, will replace the four existing TTC modules. In normal operation, the detectors, along with the surrounding electronics, will receive TTC related signals from the Central Trigger Processor (CTP). This information is forwarded to the front-end electronics of each of the ATLAS sub-detectors through an optical network via the ALTI. The interface currently produces an artificially generated pulse pattern that contains the TTC information. This paper will summarize the creation of a program that generates pulse pattern files which are used to drive ALTI. Various tests have been conducted in order to study the performance of the NSW trigger electronics while using these files. Software development and data analysis using ROOT framework were used to validate the results of these tests.

Implementation of the DCS System for the validation of MM HV Boards and the DCS System of the new BIS78 Chambers for the upgrade of muon system of the ATLAS Experiment

The ATLAS Muon Spectrometer is going through upgrades on the Phase I in order to achieve higher rates for the upcoming LHC runs. The two main projects of this Phase I upgrade are the New Small Wheels (NSW), which are expected to complement the ATLAS muon spectrometer in the end-cap regions and a smaller size project, known as BIS78 (Barrel Inner Small sectors).The NSW is expected to replace the Small Wheel (SW) and it will be installed in the ATLAS underground cavern during the summer by the end of the LHC Long Shutdown 2. This new system will be consisted by two prototype detectors, the sTGC (small Thin Gas Chambers) and the resistive Micromegas (MM).In order to cope with higher LHC luminosities, the installation of NSW will help the reduction of the trigger rate in the forward region. With half of the rate in the barrel-endcap transition region reduced by the existing TGCs, the other half of the fake trigger rate in transition region will be reduced by the new BIS78 stations. The BIS78 subproject foresees the replacement of the existing Monitored Drift Tubes (MDTs), used for the precise position measurement in this area, with muon stations formed by integrated smaller diameter tubes (sMDT) and a new generation of RPCs, capable of withstanding the higher rates and provide a robust standalone muon confirmation. The existing BIS7 and BIS8 MDT Chambers will be replaced by 16 new muon stations of one small (sMDT) chamber and two RPC triplets, and it will be the pilot project for the Phase II BI Upgrade.This work is divided into two parts. First will be presented the development and the implementation of a Detector Control System (DCS) for the HV system for the MM detectors of NSW and specifically the validation of a new type of HV Boards (A7038AP). Second, the development of the DCS for the monitoring and operation of the new sMDT chambers of the MDT Sub-System will be presented.

DIRC-like time-of-flight detector for the experiment at the Super Tau-Charm Facility

The Super Tau-Charm Facility (STCF) is a future electron-positron collider proposed in China with a peak luminosity of above 0.5 × 1035 cm-2s-1 and center-of-mass energy ranging from 2 to 7 GeV. An excellent particle identification (PID) capability is one of the most important requirements for the detector at the STCF. A 3σ π/K separation power at the momentum of up to 2 GeV/c is required within the detector acceptance. A DIRC-like time-of-flight (DTOF) detector is proposed to meet the PID requirement for the endcap region of the STCF. The conceptual design of the DTOF detector and its geometry optimization is herein presented. The PID performance of the detector is studied using Geant4 simulation. With a proper reconstruction algorithm, an overall time resolution of ∼50 ps is achieved for the detector with an optimum geometry when convoluting contributions from all other sources, including the transit time spread (TTS) of the photodetector, electronic timing accuracy, and an assumed precision (∼40 ps) of the event start time. A π/K separation power of better than 4σ at the momentum of 2 GeV/c is achieved over the entire sensitive area of the DTOF detector, thereby fulfilling the physics requirement of the PID detector for the experiment at the STCF.

Development of the front end amplifier circuit for the ATLAS ITk silicon strip detector

We present the development of the front end amplifiercircuit for the ABCStar readout ASIC designed for the upgraded ATLAS Inner Tracker (ITk) detector. The amplifier is intended to work with siliconstrip sensors of moderate length between 1.9 cm and 5.5 cm dependent on position in the detector. The final circuit is implemented in a commercial 130 nm CMOS process tolerant up to the total ionizing doses (TID) predicted for the lifetime of the detector, that is maximum of 66 Mrad (660 kGy) (Si) for the endcap region. The final architecture and the performance of the circuit is presented in the context of a long development program which started soon after the construction of the present ATLAS Semi-Conductor Tracker (SCT) detector.