System-level performance study and commissioning of TGC front-end electronics for Phase-2 upgrade of LHC-ATLAS

Abstract

The Thin Gap Chamber (TGC) of the ATLAS experiment at the LHC are responsible to provide muons trigger segments in the endcap region at the hardware trigger stage. The front-end electronics system of the TGC will be upgraded for the HL-LHC to send binary hit-map at every bunch crossing (BC) to the back-end system. Such an operation poses lots of unique challenges: hit BC identification with high efficiency, fine-tuned clock distribution, robustness for SEU, and capability of timing calibration. Accommodating these requirements, the primary processor board (PS Board) is in charge of data processing and reception of control signals from the back-end. An independent control module (JATHub) will take responsibility for FPGA configuration and clock phase monitoring of the PS Boards with an SoC-based design. Prototyping and system-level demonstration with the prototypes have been performed. This experience validates our operation and commissioning strategy of the TGC electronics system for the HL-LHC.