Emulation Platform Research Articles

Distributed Software Emulator for Cyber-Physical Analysis in Smart Grid

A smart grid is a highly complex cyber-physical electrical power system that uses two-way digital communication and intelligent embedded devices to achieve sensing, control, computation, and communication within power network. To validate the functionality, security, and reliability of such a system requires the modeling and emulation of both communication network and power network, as well as the interactions between them. In this paper, we present smart-grid common open research emulator (SCORE), a distributed software emulator for cyber-physical analysis in smart grid. SCORE integrates the emulations of both power network and communication network, and it is highlighted by the following features. First, SCORE is the first software emulation platform for smart grid, which means that the same application program running in SCORE can be directly ported to embedded devices with little or no migration issues. Second, for one smart grid instance, SCORE supports distributed emulation when the instance is in very large scale. Third, for multiple smart grid emulation instances running on different networked computers, SCORE allows them to dynamically connect or disconnect with each other in run time, such that each instance can capture its own interior system dynamics even without a prior knowledge of the entire smart grid topology.

Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic

In network-on-chip (NoC) based multi-processor system-on-chip (MPSoC) development, application profiling is one of the most crucial step during design time to search and explore optimal mapping. Conventional mapping exploration methodologies analyse application-specific graphs by estimating its runtime behaviour using analytical or simulation models. However, the former does not replicate the actual application run-time performance while the latter requires significant amount of time for exploration. To map applications on a specific MPSoC platform, the application behaviour on cycle-accurate emulated platform should be considered for obtaining better mapping quality. This paper proposes an application mapping methodology that utilizes a MPSoC prototyped in Field-Programmable Gate Array (FPGA). Applications are implemented on homogeneous MPSoC cores and their costs are analysed and profiled on the platform in term of execution time, intra-core communication and inter-core communication delays. These metrics are utilized in analytical evaluation of the application mapping. The proposed analytical-based mapping is demonstrated against the exhaustive brute force method. Results show that the proposed method is able to produce quality mappings compared to the ground truth solutions but in shorter evaluation time.

Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic

Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Due to the continuous reduction of the transistor size in electronic devices, it is becoming more and more likely for an SEU (Single Event Upset) to provoke a flip on two or more memory cells in SRAM based FPGAs, which is called a MCU (Multiple Cell Upset). Fault injection in the configuration memory of these devices has been used for many years, in order to evaluate their reliability. Emulation of these injections using the bitstream file has always been a simple, fast and cheap solution. Most of the existent SEU emulation tools do not consider the injection of MCUs, and they do not discuss the implication MCUs have on the overall failure rate of the system.In this work, bitstream based SEU emulators are updated to consider MCUs. It is discussed the necessity of injecting faults on physically adjacent cells, in order to emulate appropriately the effect of MCUs. Adjacent MCU injection has been compared theoretically with an approach considering MCUs as bunches of independent SBUs, as it is done in other emulation platforms. A Zynq-based fault injection platform has been used, in order to apply this way of emulating MCUs and validate the proposal.

S-OpenSGX: A system-level platform for exploring SGX enclave-based computing

Intel recently introduced Software Guard Extensions (SGX) to enable applications to protect their selected code and data from privileged platform software. As it draws wider attention from the security research community, an open-source emulator for SGX (OpenSGX) has been developed to allow researchers to explore the SGX environment. To the best of our knowledge, OpenSGX is currently the only publicly available SGX emulation platform; however, its system-level support is largely limited owing to its user-mode emulation. In particular, experiments that require system functionalities or device emulation cannot be conducted with the current OpenSGX. To solve this problem, we propose System-OpenSGX (S-OpenSGX), which leverages QEMU's system emulation to provide researchers with full system-level support for exploring SGX enclave-based programming. In this paper, we show the design of S-OpenSGX, including system functionalities such as scheduling, multithreading, page table handling, and SGX paging. Non-trivial issues derived from the difference between user-mode and system emulation, and our approaches to addressing them are also described. Lastly, we utilize S-OpenSGX to experiment with a new mitigation method against the data leaking attack on enclave threads and an APIC (Advanced Programmable Interrupt Controller) device modification to reduce SGX's mode switch overhead.

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications

Big Data refers to the growing challenge of turning massive, often unstructured datasets into meaningful, organized, and actionable data. As datasets grow from petabytes to exabytes and beyond, it becomes increasingly difficult to run advanced analytics, especially Machine Learning (ML) applications, in a reasonable time and on a practical power budget using traditional architectures. Previous work has focused on accelerating analytics readily implemented as SQL queries on data-parallel platforms, generally using off-the-shelf CPUs and General Purpose Graphics Processing Units (GPGPUs) for computation or acceleration. However, these systems are general-purpose and still require a vast amount of data transfer between the storage devices and computing elements, thus limiting the system efficiency. As an alternative, this article presents a reconfigurable memory-centric advanced analytics accelerator that operates at the last level of memory and dramatically reduces energy required for data transfer. We functionally validate the framework using an FPGA-based hardware emulation platform and three representative applications: Naïve Bayesian Classification, Convolutional Neural Networks, and k-Means Clustering. Results are compared with implementations on a modern CPU and workstation GPGPU. Finally, the use of in-memory dataset decompression to further reduce data transfer volume is investigated. With these techniques, the system achieves an average energy efficiency improvement of 74× and 212× over GPU and single-threaded CPU, respectively, while dataset compression is shown to improve overall efficiency by an additional 1.8× on average.

Joint Admission Control and Routing Via Approximate Dynamic Programming for Streaming Video Over Software-Defined Networking

This paper considers the optimization problem of joint admission control and routing for the video streaming service in wired software-defined networking (SDN). With the aid of the network operating system, SDN is able to support the dynamic nature of future network functions and intelligent applications. Against this changing network landscape, we rely on FlowVisor-based virtualization in the context of OpenFlow-based wired SDN to design an open optimization architecture for the joint admission control and routing, which supports flexible and agile deployment of advanced joint admission control and routing strategies. Following this architecture, we interpret the joint admission control and routing problem into the Markov decision process for maximizing the overall “revenue.” In order to solve the issue of the curses of dimensionality, we invoke the function approximation technique in the context of approximate dynamic programming to conceive an online learning framework. By applying kernel-based autonomous feature extraction into the function approximation, we develop an approximate dynamic programming-based joint admission control and routing for video streaming service, which is apt to be implemented in the proposed open architecture. An emulation platform based on FlowVisor, POX, and Mininet is constructed for demonstrating the success of the proposed solution. The experimental results are presented to show the performance improvement of the proposed scheme by comparing it with the Q-learning algorithm and open shortest path first-based benchmark scheme.

Cooperative Application Layer Joint Video Coding in the Internet of Remote Things

Recently the problem of interconnecting Internet of Things nodes when they are dispersed over wide geographical areas has been highlighted: this is the Internet of Remote Things (IoRT). It could be able to play a key role in disaster recovery scenarios (e.g., earthquakes, flash floods, terrorist attacks, etc.), where the presence of a communication infrastructure enabling video transmissions from the emergency areas is crucial. Local communications can be provided by incident area networks, while satellite communication systems can bridge the gap toward external networks. In this context, we propose a cooperative resource allocation mechanism, which exploits feedback from links conditions and knowledge of the adaptive coding, allowing a higher quality and more fair experience for all nodes of the IoRT transmitting videos. We implemented each element of the mentioned scenario over an emulation platform to prove the concept and show the obtained benefits.

SDN-SPS: Semi-Physical Simulation for Software-Defined Networks

Nowadays, software-defined networking (SDN) is one of the key technologies promoting the development of the next generation network. In addition, simulating and building the SDN real network is one of the most important approaches to do SDN research. However, there are many aspects that limit the test platform-based experiment and the traditional software-only simulation, such as the various demands of network, complex applications, and flexible network architecture. Combining test platform with the software-only simulation, this paper proposes a new hardware-in-the-loop emulation: to emulate a SDN. We use the system-in-the-loop technology of OPNET to build the SDN hardware-in-the-loop emulation platform. The emulation test platform includes the sensor network part, all of which will use the software simulation, together with the transmission network and the cloud data center both of which will use the real network. We run the simulation to generate a few applications in the cloud data center, and then collect the data through the transmission network and the sensor network, which makes these applications share the sensing data. This paper proves that the simulation test platform of hardware-in-the-loop can achieve energy efficiency under the demand of QoS.

Design, Characterization, and Application of a Field-Programmable Thermal Emulation Platform

This paper presents an on-chip digitally programmable thermal coupling emulation framework, referred to as the field-programmable thermal emulator (FPTE), for online characterization of power pattern, time-varying thermal field, and associated changes in the electrical characteristics of the transistors. A test chip was designed in 130-nm CMOS to validate the test structure. The measurement results demonstrated the ability of FPTE to emulate various power patterns and capture the effects on temperature and circuit performance. The test chip is used to explore and identify thermal coupling. The potential application of FPTE moves beyond thermal package tests and is capable of being used as chip-level thermal condition prediction and management infrastructure.

Analysis and Influence of Economical Decisions on the Quality of Experience of OTT Services

In a context in which the Internet provides a platform used to distribute contents, new actors have emerged in the business of multimedia services, who have taken advantage of this new platform to deliver services at lower cost. However, the Internet does not provide a reliable platform to distribute content, which justifies the development of technology that ensures high levels of quality to the end user of the service. This work presents the advances developed in this direction in the context of the Celtic+ Project NOTTS: first, a new Quality of Experience (QoE) evaluation framework that incorporates economical variables in the analysis; second, the implementation of the before mentioned framework in order to analyze how the user's decisions impact of the QoE; and lastly, an emulation platform for Over-The-Top Services (OTT), used to emulate the behavior of these services in real Internet scenarios and to apply the implementation of the framework proposed.

Evaluating fault tolerance on asymmetric multicore systems‐on‐chip using iso‐metrics

The end of Dennard scaling has promoted low power consumption into a first-order concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, reliability. These limitations would make them unsuitable for HPC systems and datacenters. To demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM's big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the study describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.

Rapid prototyping of Networks-on-Chip on multi-FPGA platforms

Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms.

EmuStack: An OpenStack-Based DTN Network Emulation Platform (Extended Version)

With the advancement of computing and network virtualization technology, the networking research community shows great interest in network emulation. Compared with network simulation, network emulation can provide more relevant and comprehensive details. In this paper, EmuStack, a large-scale real-time emulation platform for Delay Tolerant Network (DTN), is proposed. EmuStack aims at empowering network emulation to become as simple as network simulation. Based on OpenStack, distributed synchronous emulation modules are developed to enable EmuStack to implement synchronous and dynamic, precise, and real-time network emulation. Meanwhile, the lightweight approach of using Docker container technology and network namespaces allows EmuStack to support a (up to hundreds of nodes) large-scale topology with only several physical nodes. In addition, EmuStack integrates the Linux Traffic Control (TC) tools with OpenStack for managing and emulating the virtual link characteristics which include variable bandwidth, delay, loss, jitter, reordering, and duplication. Finally, experiences with our initial implementation suggest the ability to run and debug experimental network protocol in real time. EmuStack environment would bring qualitative change in network research works.

Fast and accurate FPGA-based framework for processor architecture vulnerability analysis

This paper presents a fast, accurate, and flexible FPGA-based fault emulation platform, namely FARAVAM that can be exploited for AVF analysis in modern microprocessors. The proposed approach provides fault injection capabilities supporting automatic modification of post-synthesis net-lists and introduces a highly controllable and observable transient fault analysis environment. The presented vulnerability analysis platform using both exhaustive and random fault emulation approaches, provides useful information for identifying areas threatening reliability to make processors more fault tolerant. We applied our platform for extracting the best trade-offs between precision and speed up in vulnerability analysis of MIPS processor. The experimental results indicate that in addition to having high precision we obtain about seven orders of magnitude speed up in comparison with simulation based vulnerability analysis techniques.

Post-FEC Performance of Nondifferential Transmission in the Presence of Phase Noise

We assess the impact of phase noise on the bit error rate (BER) after forward error correction (FEC) decoding (post-FEC BER) and on the error distribution in the case of differential and nondifferential (ND) transmission. We show that the use of pilot symbols enables reliable ND transmission and relaxes the requirements on bit-interleaving, and therefore, on the end-to-end latency. Further, we provide guidelines for the design and choice of carrier recovery and FEC parameters to obtain good performance in typical scenarios. All presented results are achieved through the use of a high-speed system emulation platform based on field-programmable gate arrays and thus achieve high reliability even for very low post-FEC BER.

Scalable Synchrophasors Communication Network Design and Implementation for Real-Time Distributed Generation Grid

There has been a growing interest in the deployment of phasor measurement units (PMUs) not only in high-voltage transmission, but in lower-voltage distribution systems. For a distributed generation (DG) grid, this would require deployment of PMUs at critical locations, which implies accurate phase measurement with the support of a low delay, highly reliable network infrastructure. In the absence of such a network, the most cost-effective solution would be to consider a wireless network to support centralized control for situational awareness in the transmission, as well as the DG grid environment. Therefore, the main objective in this paper is to design and implement a scalable synchrophasor network using wireless LAN technology to assess network performance and requirements under real-world conditions. To achieve this, we have designed an emulation platform that can support physical and medium access control layers. The data communication at the application is based on the IEEE C37.118-2011-2 Standard. By considering a hierarchical network architecture for our testbed implementation, we propose an efficient method to reduce bandwidth, as well as provide capabilities for control and management at each hierarchical level. In addition, an efficient tree-based multihop routing protocol has been designed to match a specific distribution feeder structure. The testbed is then used to access different network configurations under various test conditions.

R2C2

Rack-scale computers, comprising a large number of micro-servers connected by a direct-connect topology, are expected to replace servers as the building block in data centers. We focus on the problem of routing and congestion control across the rack's network, and find that high path diversity in rack topologies, in combination with workload diversity across it, means that traditional solutions are inadequate. We introduce R2C2, a network stack for rack-scale computers that provides flexible and efficient routing and congestion control. R2C2 leverages the fact that the scale of rack topologies allows for low-overhead broadcasting to ensure that all nodes in the rack are aware of all network flows. We thus achieve rate-based congestion control without any probing; each node independently determines the sending rate for its flows while respecting the provider's allocation policies. For routing, nodes dynamically choose the routing protocol for each flow in order to maximize overall utility. Through a prototype deployed across a rack emulation platform and a packet-level simulator, we show that R2C2 achieves very low queuing and high throughput for diverse and bursty workloads, and that routing flexibility can provide significant throughput gains.

Routing centralization across domains via SDN: A model and emulation framework for BGP evolution

The Border Gateway Protocol (BGP) was designed almost three decades ago and has many limitations relating to its fully distributed nature, policy enforcement capabilities, scalability, security and complexity. For example, the control plane can take several minutes to converge after a routing change; this may be unacceptable for real-time network services. Despite many research proposals for incremental improvements and clean-slate redesigns of how inter-domain routing should work, BGP is likely one of the most ossified protocols of the Internet architecture and it has not retrofitted the proposed ideas. In this work, we propose a radical, incrementally deployable Internet routing paradigm in which the control plane of multiple networks is logically centralized. This follows the Software Defined Networking (SDN) paradigm, although at the inter-domain level involving multiple Autonomous Systems (AS). Multi-domain SDN centralization can be realized by outsourcing routing functions to an external contractor, which provides inter-domain routing services facilitated through a multi-AS network controller. The proposed model promises to become a vehicle for evolving BGP and uses the bird’s eye view over several networks to benefit aspects of inter-domain routing, such as convergence properties, policy conflict resolution, inter-domain troubleshooting, and collaborative security. In addition to the proposed paradigm, we introduce a publicly available emulation platform built on top of Mininet and the Quagga routing software, for experimenting on hybrid BGP–SDN AS-level networks. As a proof of concept, we focus specifically on exploiting multi-domain centralization to improve BGP’s slow convergence. We build and make publicly available a first multi-AS controller tailored to this use case and demonstrate experimentally that SDN centralization helps to linearly reduce BGP convergence times and churn rates with expanding SDN deployments.