Emulation Of Circuits Research Articles

Fast Emulation of Fermionic Circuits with Matrix Product States.

We describe a matrix product state (MPS) extension for the Fermionic Quantum Emulator (FQE) software library. We discuss the theory behind symmetry-adapted MPSs for approximating many-body wave functions of spin-1/2 Fermions, and we present an open-source, MPS-enabled implementation of the FQE interface (MPS-FQE). The software uses the open-source pyblock3 and block2 libraries for most elementary tensor operations, and it can largely be used as a drop-in replacement for FQE that allows for more efficient but approximate emulation of larger Fermionic circuits. Finally, we show several applications relevant to both near-term and fault-tolerant quantum algorithms where approximate emulation of larger systems is expected to be useful: characterization of state preparation strategies for quantum phase estimation, the testing of different variational quantum eigensolver ansätze, the numerical evaluation of Trotter errors, and the simulation of general quantum dynamics problems. In all these examples, approximate emulation with MPS-FQE allows us to treat systems that are significantly larger than those accessible with a full statevector emulator.

Near-field coupling and wireless signal transmission using a magnetoelectric laminated composite antenna

Magnetoelectric (ME) antennas utilize the direct or converse ME effects at acoustic resonance to receive or transmit electromagnetic (EM) signals, making ultra-compact antennas feasible. This work presents a miniaturized ME antenna working at very low frequency (VLF) band. A piezoelectric wafer and magnetostrictive foils are bonded together to form the 12×2.1×0.08 cm3 ME antenna. The near-field coupling between the ME antenna and magnetic rod coil has been measured to verify the reciprocity. The proposed entire circuit simulation models agree well with the experimental results, explaining the maximum power gap and frequency offset phenomenon. In addition, both practical and simulation results confirm that near-field coupling depends on mutual inductance rather than EM radiation. Based on the emulation of circuits, L-section impedance matching networks are introduced to improve the original power transmission coefficient by 21 dB. The ME antenna is lightweight, wide-band, and easy to match compared with a conventional coil.

A Review of Neural Network-Based Emulation of Guitar Amplifiers

Vacuum tube amplifiers present sonic characteristics frequently coveted by musicians, that are often due to the distinct nonlinearities of their circuits, and accurately modelling such effects can be a challenging task. A recent rise in machine learning methods has lead to the ubiquity of neural networks in all fields of study including virtual analog modelling. This has lead to the appearance of a variety of architectures tailored to this task. This article aims to provide an overview of the current state of the research in neural emulation of analog distortion circuits by first presenting preceding methods in the field and then focusing on a complete review of the deep learning landscape that has appeared in recent years, detailing each subclass of available architectures. This is done in order to bring to light future possible avenues of work in this field.

A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum computers do not have the capability to correct errors caused by environmental noise, so that it is difficult to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in digital computers is essential. However, emulation of large quantum circuits requires enormous amount of computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up to 30 qubits using two FPGAs. According to the measured results, we have achieved 23.6 ~ 24.5 times speed-up compared to a fully optimized 24-core CPU emulator.

Emulation of Circuits under Test Using Low-Cost Embedded Platforms

Electrical engineering education requires the development of the specific ability and skills to address the design and assembly of practical electronic circuits, as well as the use of advanced electronic instrumentation. However, for electronic instrumentation courses or any other related specialty that pursues to gain expertise testing a physical system, the circuit assembly process itself can represent a bottleneck in a practical session. The time dedicated to the circuit assembly is subtracted both to the measurements and the final decision-making time. Therefore, the student’s practical experience is limited. This article presents a reconfigurable physical system based on the Arduino™ shield pin-out, which (after specific programming) can virtually behave as a device under test to carry out measurement procedures on it, emulating any system or process. Although it has been mainly oriented to the Arduino boards, it is possible to add different control devices with a connector compatible. The user does not need to assemble any circuit. Our approach does not only pursue the correct instrument handling as a goal, but it also immerses the student in the context of the functional theory of the proposed circuit under test. Consequently, the same emulation platform can be utilized for other techno-scientific specialties, such as electrical engineering, automatic control systems or physics courses. Besides that, it is a compact product that can be adapted to the needs of any teaching institution.

Toward Neuromorphic Photonic Networks of Ultrafast Spiking Laser Neurons

We report on ultrafast artificial laser neurons and on their potentials for future neuromorphic (brainlike) photonic information processing systems. We introduce our recent and ongoing activities demonstrating controllable excitation of spiking signals in optical neurons based upon vertical-cavity surface emitting lasers (VCSEL-Neurons). These spiking regimes are analogous to those exhibited by biological neurons, but at sub-nanosecond speeds (>7 orders of magnitude faster). We also describe diverse approaches, based on optical or electronic excitation techniques, for the activation/inhibition of sub-ns spiking signals in VCSEL-Neurons. We report our work demonstrating the communication of spiking patterns between VCSEL-Neurons toward future implementations of optical neuromorphic networks. Furthermore, new findings show that VCSEL-Neurons can perform multiple neuro-inspired spike processing tasks. We experimentally demonstrate photonic spiking memory modules using single and mutually coupled VCSEL-Neurons. Additionally, the ultrafast emulation of neuronal circuits in the retina using VCSEL-Neuron systems is demonstrated experimentally for the first time to our knowledge. Our results are obtained with off-the-shelf VCSELs operating at the telecom wavelengths of 1310 and 1550 nm. This makes our approach fully compatible with current optical network and data center technologies, hence offering great potentials for future ultrafast neuromorphic laser-neuron networks for new paradigms in brain-inspired computing and artificial intelligence.

Real-time emulation of block-based analog circuits on an FPGA

In order to provide a real-time emulation platform for analog signal processing circuits, we propose a block based approach with a constant worst case runtime. We evaluate an FPGA-based implementation of this approach by comparing its output for different test cases to a non-real-time SPICE simulation. The implementation runs at a sampling rate of 88.2 kHz and features roundtrip times as low as 0.096 ms (12 bit ADC) and 0.190 ms (16 bit ADC). A completely automated process is introduced for fitting model parameters of filters and various nonlinear blocks. The fitting process is evaluated based on 35 block examples with R2 values ranging from 0.967 to 0.999. For complex filter structures we were able to replicate the frequency responses predicted by a SPICE AC analysis accurately. Furthermore we compare measured transient responses of the FPGA-based emulation with SPICE and discuss advantages and disadvantages of the approach.

Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

SummaryThis paper presents a semi‐automated word‐length optimization framework to reduce field‐programmable gate array (FPGA) resource utilization for FPGA‐based pre‐silicon test emulation of analog and mixed signal circuits while achieving the desired accuracy and overcoming long optimization time. Although high‐level behavioral models exist for modeling analog and mixed signal circuits, these comprise many complex differential equations which cannot be realized implicitly using Boolean logic (which is the basic functional block of an FPGA) on an FPGA. So, a more convenient way is explored to map analog circuits into digital domain by converting them into fixed‐point architectures because of its advantage of manipulating data with lower word‐length. To address the loss of accuracy due to finite word‐length effects and limited reconfigurable resources, word‐lengths are optimized under the constraint of given performance metrics. The proposed technique built in MATLAB/Simulink environment with Xilinx System Generator support is illustrated with the help of a case study of a peak‐current‐mode‐controlled buck‐type switching converter implemented on Xilinx Virtex™‐5 FPGA. To illustrate the applicability of this environment for pre‐silicon test development, well‐accepted fault models are emulated with the help of non‐ideal model of a buck converter. The emulation results are seen to be close to that of a post‐fabricated power converter in the presence of faults. Experimental results show that FPGA resource utilization can be reduced significantly while achieving the desired performance accuracy under the constraint of multiple error metrics. Copyright © 2017 John Wiley & Sons, Ltd.

Hardware emulation of quantum circuits based on Toffoli gates

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.

Emulation of Operational Amplifiers and Diodes in Audio Distortion Circuits

This brief presents a generic model to emulate distortion circuits using operational amplifiers and diodes. Distortion circuits are widely used for enhancing the sound of guitars and other musical instruments. This brief introduces a new model for an ideal operational amplifier that does not include implicit equations and is thus suitable for implementation using wave digital filters (WDFs). Furthermore, a novel WDF model for a diode is proposed using the Lambert W function. A comparison of output signals of the proposed models to those obtained from a reference simulation using SPICE shows that the distortion characteristics are accurately reproduced over a wide frequency range. Additionally, the proposed model enables real-time emulation of distortion circuits using ten multiplications, 22 additions, and two interpolations from a lookup table per output sample.

Low Power Dissipation and High Fault Coverage Fault emulation of synchronous sequential circuits on FPGA

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. This paper presents a low hardware overhead test pattern generator (TPG) for Fault Emulation that can reduce switching activity in circuits under test (CUTs) during testing and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed test pattern generation decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed method is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT- RTPG patterns are applied. The proposed approach allows simulation speed-up of 40-500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.

FPGA-based fault emulation of synchronous sequential circuits

A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40–500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.