Emulation Environment Research Articles

Real-Time Hardware-in-the-Loop Simulation of Permanent-Magnet Synchronous Motor Drives Under Stator Faults

Hardware-in-the-loop (HIL) testing methods can facilitate the development of control strategies in a safe and inexpensive environment particularly when extreme operating conditions such as faults are considered. HIL methods rely on accurate real-time emulation of the equipment under investigation. However, no validated tools for real-time emulation of electrical drives under fault conditions are available. This paper describes the implementation of a high-fidelity real-time emulator of a permanent-magnet synchronous motor drive in a platform suitable for HIL tests. The emulator is capable of representing the drive operation under both healthy conditions and during interturn stator winding faults. Nonlinearities due to saturation, higher order harmonics, slotting effects, etc., are accounted for using four-dimensional look-up tables (LUTs) obtained by finite element analysis. The proposed model is computationally efficient and capable of running in real time in a field programmable gate array platform and is validated against simulations and experimental results in a wide range of operating conditions. Potential applications of the proposed emulation environment to the development of drive control, fault detection, and diagnostic algorithms are proposed.

How Far Can We Go? Towards Realistic Software-Defined Wireless Networking Experiments

Software-Defined Wireless Networking (SDWN) is an emerging approach based on decoupling radio control functions from the radio data plane through programmatic interfaces. Despite diverse ongoing efforts to realize the vision of SDWN, many questions remain open from multiple perspectives such as means to rapid prototype and experiment candidate software solutions applicable to real world deployments. To this end, emulation of SDWN has the potential to boost research and development efforts by re-using existing protocol and application stacks while mimicking the behavior of real wireless networks. In this article, we provide an in-depth discussion on that matter focusing on the Mininet-WiFi emulator design to fill a gap in the experimental platform space. We showcase the applicability of our emulator in an SDN wireless context by illustrating the support of a number of use cases aiming to address the question on how far we can go in realistic SDWN experiments, including comparisons to the results obtained in a wireless testbed. Finally, we discuss the ability to replay packet-level and radio signal traces captured in the real testbed towards a virtual yet realistic emulation environment in support of SDWN research.

Performance Analysis of Applying Load Balancing Strategies on Different SDN Environments

Software-Defined Network (SDN) is considered a breakthrough to the global network. It plays an important role in performance improvement and network optimization. SDN is a new mechanism for managing and designing networks rather than the current traditional network system which does not afford more services and higher data rates; therefore, we analyze the effect of applying load balancing techniques and its importance in different SDN environments. In this paper, we propose a dynamic server load balancing technique in SDN architecture. Hence, we implement a server Connection-based load balancing technique and evaluate its performance with a static Round-robin and Random-based in both mininet emulation environment and Raspberry Pi OpenFlow-enabled switch using Ryu OpenFlow controller. The performance of the proposed algorithm is compared with Round-robin and random distribution of clients' requests. The results show that the proposed technique achieves more reliability and higher resource utilization than the Round-robin and Random-based load balancing strategies. In addition, the proposed scheme exhibits more scalability and low-cost characteristics.Software-Defined Network (SDN) is considered a breakthrough to the global network. It plays an important role in performance improvement and network optimization. SDN is a new mechanism for managing and designing networks rather than the current traditional network system which does not afford more services and higher data rates; therefore, we analyze the effect of applying load balancing techniques and its importance in different SDN environments. In this paper, we propose a dynamic server load balancing technique in SDN architecture. Hence, we implement a server Connection-based load balancing technique and evaluate its performance with a static Round-robin and Random-based in both mininet emulation environment and Raspberry Pi OpenFlow-enabled switch using Ryu OpenFlow controller. The performance of the proposed algorithm is compared with Round-robin and random distribution of clients' requests. The results show that the proposed technique achieves more reliability and higher resource utilization than the Round-robin and Random-based load balancing strategies. In addition, the proposed scheme exhibits more scalability and low-cost characteristics.

Living with congestion: Digital Fountain based Communication Protocol

In this paper, we propose a networking paradigm built upon a fountain code based data transfer mechanism. We advocate that, instead of controlling the congestion as it is applied in recent Internet by the Transmission Control Protocol (TCP), we can utilize congestion and neglect control algorithms with all of their drawbacks. We present our envisioned network architecture relying on a novel transport protocol called Digital Fountain based Communication Protocol (DFCP) and highlight some potential application areas. We have implemented DFCP in the Linux kernel and we provide its validation results gained from three different testing platforms including our laboratory testbed, the Emulab network emulation environment and the ns-2 network simulator. Moreover, we present and discuss a comprehensive performance evaluation of DFCP in comparison with widely used TCP versions.

Tools for Modeling Exemplary Network Infrastructures

The article deals with the selection of a suitable environment for the creation of patterns and functional schemes for deployment in virtualization environments OpenStack. There are several programs that offer possibility of network modeling processes. Several can be used in OpenStack. The disadvantage, however, is the impossibility of direct testing of the proposed structure of the ideological offline. Emulation environment of different open-source programs allow the use of simple hardware resources for testing of future production system offline.

Experimental assessment of a cognitive mechanism to reduce the impact of outdated TEDs in optical networks

We have recently proposed and demonstrated, by means of simulation, the benefits of a simple yet effective cognitive technique to enhance stateless Path Computation Element algorithms with the aim of reducing the connection blocking probability when relying on a potentially non-up-to-date traffic engineering database. In this paper, we employ that technique, called elapsed time matrix (ETM), in the framework of the CHRON (Cognitive Heterogeneous Reconfigurable Optical Network) architecture and, more importantly, validate and analyze its performance in an emulation environment (rather than in a simulation environment) supporting impairment-aware lightpath establishment. Not only dynamic lightpath establishment on demand has been studied, but also restoration processes when facing optical link failures. Emulation results demonstrate that ETM reduces the blocking probability when establishing lightpaths on demand, and increases the percentage of successful restorations in case of optical link failure. Moreover, the use of that technique has little impact on lightpath setup time and lightpath restoration time, respectively.

WiSeREmulator: An emulation framework for wireless structural health monitoring

Many competing approaches exist in evaluating sensor network solutions differing by levels of ease of use, cost, control, and realism. Existing work concentrates on simulating network protocols or emulating processing units at the machine cycle level. However, little has been done to emulate the sensors and the physical environments that they monitor. The main contribution of this work is the design of WiserEmulator, an emulation framework for structural health monitoring, which gracefully balances the trade-offs between realism, controllability, and cost. WiserEmulator consists of two main components - a testbed of wireless sensor nodes and a software emulation environment. To emulate the excitation and response of piezo-electric transducers, as well as the wave propagation inside concrete structures, the COMSOL Multi-Physics software was utilized. Digitized sensing output from COMSOL was played back via a multi-channel Digital-to-Analog Converter (DAC) connected to the wireless sensor testbed. In addition to the emulation of concrete structures, WiSeREmulator also allows users to choose prestored data collected from field experiments and synthesized data. A user-friendly Graphical User Interface (GUI) was developed that facilitates intuitive configurations of experimental settings, control of the on-set and progression of the experiments, and real-time visualization of experimental results. We have implemented WiSeREmulator in MATLAB. This work advances the state of the art in providing low cost solutions to evaluating Cyber Physical Systems such as wireless structural health monitoring networks.

Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety–critical designs

Steadily decreasing transistor sizes and new multi beam laser attacks lead to an increasing amount of multi-bit fault occurrences, e.g., during fault attacks against cryptographic implementations. Therefore, multi-bit fault injection becomes more important during security and safety verification. Fault injection techniques which are applicable during the development cycle of a device are based on either software implementations, e.g. formal methods and simulations, or fault emulation environments in hardware. So far, simulations provide the best configurability whereas fault emulation environments provide the best performance in terms of run time. This contribution presents an FPGA-based emulation environment that combines the advantages of both simulation-based and emulation-based environments. To the best of our knowledge, we are the first to achieve this. Permanent and transient multi-bit faults are configurable at run time where the selection of a fault model, the configuration of the injection time and fault duration is supported without the need for re-synthesizing the design. We propose three measures for performance optimization allowing us to support all the fault configuration capabilities at run time without performance penalty. Experimental results are provided for a hardened 8051-like microprocessor showing that the presented emulation environment reaches the theoretical optimal performance for a wide range of fault configurations using our proposed optimizations.

Experimental validation of resilient tree-based greedy geometric routing

Geometric routing is an alternative for IP routing based on longest prefix matching. Using this routing paradigm, every node in the network is assigned a coordinate and packets are forwarded towards their intended destination following a distance-decreasing policy (greedy forwarding). This approach makes the routers significantly more memory-efficient compared to the current IP routers. In this routing, greedy embeddings are used to guarantee a 100% successful delivery to every destination in the network. Most of the existing proposals lack resiliency mechanisms to react efficiently to network changes. We propose a distributed algorithm to calculate a greedy embedding based on a spanning tree of the network. In this algorithm, nodes are triggered to re-calculate their coordinates upon a change in the topology such as link or node failures. The advantage of this approach is that it recovers from topology failures within a very short period of time. We further extend the algorithm to generate backups to apply protection in distributed setups. Different trade-offs and trends of re-convergence for geometric routing have been evaluated in an emulation environment. Realistic results are achieved through emulation as no model or abstraction is involved. The proposed routing scheme is implemented in Quagga routing software and new elements are developed in Click modular router to enable greedy forwarding. For the first time, the performance of this scheme is evaluated through emulation on a large topology of 1000 nodes and the results are compared with BGP. The experimental results indicate that the proposed scheme has interesting characteristics in terms of convergence time upon a change in the network topology.

Interaction Traces Mining for Efficient System Responses Generation

Software service emulation is an emerging technique for creating realistic executable models of server-side behaviour. It is particularly useful in quality assurance and DevOps, replicating production-like conditions for large-scale enterprise software systems. Existing approaches can automatically build client-server and server-server interaction models of complex software systems directly from analysis of service interaction trace data. However, when these interaction traces become large, searching an entire trace library to generate a run-time responses can become very slow. In this paper we describe a new technique that utilises data mining, specifically clustering algorithms, to pre-process large amounts of recorded interaction trace data. With the obtained clusters we facilitate efficient yet well-formed runtime response generation in our Enterprise System emulation environment. We evaluate our approach using two common application-layer protocols: LDAP and SOAP. Our experimental results show that by utilising clustering techniques in the pre-processing step, the response generation time can be reduced by 99% on average compared with existing approaches.

Probabilistic inference-based service level objective-sensitive virtual network reconfiguration

Network virtualization enables multiple service providers to share the same physical infrastructure, and allows physical substrate network (SN) resources to be used in the form of a virtual network (VN). However, there are many obstacles to the application of this technology. One of the more challenging is the reconfiguration of SN-embedded VNs to adapt to varying demands. To address this problem, we propose a service level objective (SLO)-sensitive VN reconfiguration (VNR) method. A Bayesian network learning and probabilistic reasoning-based approach is proposed to automatically localise reconfiguration points and generate VN resource requests. To determine an optimal reconfiguration solution, we design a heuristic VNR algorithm with a virtual node and virtual link swapping strategy. We validate and evaluate this algorithm by conducting experiments in a high-fidelity emulation environment. Our results show that the proposed approach can effectively reconfigure a VN to adapt to a changed SLO. A comparison shows that our reconfiguration algorithm outperforms existing solutions.

Ideal Forward Error Correction Codes for High-Speed Rail Multimedia Communications

In recent years, application-layer forward error correction (AL-FEC), particularly rateless AL-FEC, has received much attention due to its superior performance in both transmissional and computational efficiency. Rateless AL-FEC (e.g., Raptor code or Luby transform (LT) code) can protect a large data block with an overhead somewhat close to ideal codes. In the meantime, its data processing rates of both encoding and decoding are quite efficient even in software implementations. However, we found that conventional rateless AL-FEC schemes may not be the best candidates when considering streaming over Worldwide Interoperability for Microwave Access (WiMAX) networks for high-speed rail reception in Taiwan. In this paper, we propose a new ideal AL-FEC scheme based on the Chinese remainder theorem (CRT) to facilitate streaming service delivery for high-speed rail reception. The proposed scheme can support the rateless property, but it requires less transmission overhead than conventional rateless codes. Although it requires higher computational cost than conventional rateless codes, the cost is affordable for commodity laptops. In addition to measuring the FEC computation, storage, and decoder overhead, we also evaluate its performance in an emulation environment for simulating high-speed rail reception over WiMAX networks. The emulation result shows that the proposed scheme can achieve the same error protection as Raptor codes, but it requires less transmission overhead, which is suitable for protecting data transmission over bandwidth-limited high-mobility erasure channels.

QoS Estimation and Prediction of Input Modality in Degraded IP Networks

This paper evaluates the impact of combined transcoding and packet loss degradation on speech as input for the interactive voice response service (IVR) and proposes a method for classification of user input according to speech quality. Careful optimization of a communication system and all of its segments need to be considered, as the quality of the user's experience is becoming a more prominent part of the overall acceptance and desirability of modern service. Within our research, emulation environment was developed and the behavior of IVR analyzed under different packet loss and transcoding conditions. A set of frequently-used vocoders was tested on its performance with an automatic speech recognition module under degraded conditions. Further, quality estimation classifier was proposed, based on the Gaussian mixture models to determine best user's input modality. Various train and test parameters were investigated to provide more detailed insight of input quality estimation for IVR service working under error prone conditions.

Managing the life cycle of Java Card applets in other Java virtual machines

Purpose – The purpose of this paper is to address the design, implementation, performance and limitations of an environment that emulates a secure element for rapid prototyping and debugging. Today, it is difficult for developers to get access to a near field communication (NFC)-secure element in current smartphones. Moreover, the security constraints of smartcards make in-circuit emulation and debugging of applications impractical. Therefore, an environment that emulates a secure element brings significant advantages for developers. Design/methodology/approach – The authors' approach to such an environment is the emulation of Java Card applets on top of non-Java Card virtual machines (e.g. Android Dalvik VM), as this would facilitate the use of existing debugging tools. As the operation principle of the Java Card VM is based on persistent memory technology, the VM and applications running on top of it have a significantly different life cycle compared to other Java VMs. The authors evaluate these differences and their impact on Java VM-based Java Card emulation. They compare possible strategies to overcome the problems caused by these differences, propose a possible solution and create a prototypical implementation to verify the practical feasibility of such an emulation environment. Findings – While the authors found that the Java Card inbuilt persistent memory management is not available on other Java VMs, they present a strategy to model this persistence mechanism on other VMs to build a complete Java Card run-time environment on top of a non-Java Card VM. Their analysis of the performance degradation in a prototypical implementation caused by additional effort put into maintaining persistent application state revealed that the implementation of such an emulation environment is practically feasible. Originality/value – This paper addresses the problem of emulating a complete Java Card run-time environment on top of non-Java Card virtual machines which could open and significantly ease the development of NFC secure element applications.

Exploiting content centric networking to develop topic-based, publish–subscribe MANET systems

Mobile Ad-hoc NETworks (MANETs) connect mobile wireless devices without an underlying communication infrastructure. Communications occur in a multi-hop fashion, using mobile devices as routers. Several MANET distributed applications require to exchange data (GPS position, messages, pictures, etc.) by using a topic-based publish–subscribe interaction. Participants of these applications can publish information items on a given topic (identified by a name) and can subscribe to a topic to receive the related published information. An efficient dissemination of publish–subscribe data in MANET environments demands for robust systems, able to face radio resource scarcity, network partitioning, frequent topology changes. Many MANET publish–subscribe systems have been proposed so far in the literature assuming an underlying TCP/IP network.In this paper, we discuss the benefits of building a MANET publish–subscribe system exploiting Content Centric Networking (CCN) technology, rather than TCP/IP. We show how CCN functionality, such as in-network caching and multicasting can be used to achieve an efficient and reliable data dissemination in MANET environments, including the support of delay tolerant delivery. We present different design approaches, describe our topic-based publish–subscribe CCN system, and report the results of a performance evaluation study carried out with real software in an emulated environment. The emulation environment is based on Linux virtual machines. The performance evaluation required also a CCN MANET routing engine, which we developed as a plug-in of the OLSR Linux daemon.

Keyflow: a prototype for evolving SDN toward core network fabrics

The large bulk of packets/flows in future core networks will require a highly efficient header processing in the switching elements. Simplifying lookup in core network switching elements is capital to transport data at high rates and with low latency. Flexible network hardware combined with agile network control is also an essential property for future software-defined networking. We argue that only further decoupling between the control and data planes will unlock the flexibility and agility in SDN for the design of new network solutions for core networks. This article proposes a new approach named KeyFlow to build a flexible network-fabricbased model. It replaces the table lookup in the forwarding engine by elementary operations relying on a residue number system. This provides us tools to design a stateless core network by still using OpenFlow centralized control. A proof of concept prototype is validated using the Mininet emulation environment and OpenFlow 1.0. The results indicate RTT reduction above 50 percent, especially for networks with densely populated flow tables. KeyFlow achieves above 30 percent reduction in keeping active flow state in the network.

Emulation Environment for Nationwide Sensor Network

Emulation Environment for Nationwide Sensor Network

Emulation environment for automobile automatic climate control

This study presents the development of a simulation platform for evaluating climate control strategies for automobiles. Unified modeling language-based use-case diagrams and statechart diagrams are employed to model the functionalities and dynamic behaviors, respectively, of a typical automatic air-conditioning system. With these two modeling diagrams as blueprints of the simulation target, a general simulation platform is implemented on Matlab/Simulink. Given a tested climate control algorithm and environment conditions, simulation results in terms of temperature and relative humidity in the car compartment can be visually presented on an implemented graphic user interface of a psychrometric chart. With its flexibility to replace control algorithms and to change testing parameters, the implemented platform has been utilized to test the control results of an enthalpy-based control algorithm, robustness of the same control algorithm at different initial conditions, and comparison of two different control algorithms.

Crack Depth Estimation by Using a Multi-Frequency ECT Method

In many industrial application fields as manufacturing, quality control, and so on, it is very important to highlight, to locate, and to characterize the presence of thin defects (cracks) in conductive materials. The characterization phase tries to determine the geometrical characteristics of the thin defect namely the length, the width, the height, and the depth. The analysis of these characteristics allows the user in accepting or discarding realized components and in tuning and improving the production chain. The authors have engaged this line of research with particular reference to non-destructive testing applied to the conductive material through the use of eddy currents. They realized methods and instruments able to detect, locate, and characterize thin defects. In this paper, a novel measurement method able to improve the characterization of the crack depth is proposed. It is based on the use of a suitable multi-frequency excitation signals and of digital signal processing algorithms. Tests carried out in an emulation environment have shown the applicability of the method and have allowed the tuning of the measurement algorithm. Tests carried out in a real environment confirm the goodness of the proposal.

Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time

Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).