Emitter Edge Research Articles

Effects of dislocations in silicon transistors with implanted emitters

Silicon bipolar transistors have been made by substituting a shallow phosphorus implanation for the standard emitter deposition used in the manufacture of linear integrated circuits. The implantation was followed by a high temperature heat treatment (drive-in), which caused the implanted ions to diffuse deeper into the semiconductor to give emitter/base junction depths of typically 1.8 μm. When the high temperature heat treatment was performed in an oxidising atmosphere, the resulting transistors had lower gains and higher emitter/base leakages than the comparable standard diffused transistors. However, if an 1180°C drive-in, in an inert atmosphere, was performed prior to the oxidation drive-in, high gains and low emitter/base leakages were obtained. Alternatively, if the oxidation drive-in was omitted, and instead an inert drive-in performed at any temperature between 1000 and 1180°C, high gains and low emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were caused by emitter edge dislocations intersection the emitter/base junction around the perimeter of the emitter. A mechanism is suggested to describe the formation of the emitter edge dislocations.

Dislocation propagation and emitter edge defects in silicon wafers

Some transistor defects show a tendency to occur near the edges of emitters. Like ’’area defects’’, these ’’edge defects’’ occur in silicon wafers in a distribution pattern reminiscent of thermal-stress-induced dislocations. A peculiar feature is that often a number of edge defects which are close replicas of one another occur in a string, each in one of the neighboring emitters. Such edge defects are preponderant in transistors having silicon nitride surface films. In our proposed model, these emitter edge defects are generated when thermal-stress-induced dislocations glide through a row of emitters and interact with the emitter edge stresses, thereby, and under appropriate conditions, casting off small dislocation half-loops which straddle the edges. The model is shown to be consistent with all the observed phenomena pertaining to the emitter edge defect. To provide a foundation for the discussion of the finer details of the emitter edge defects, we also present an analysis of the nature and distribution of thermally induced dislocations, itself a topic of general interest.

Propagation of residual dislocations during silicon epitaxy

The propagation of residual dislocations during silicon epitaxy was studied by means of etching and scanning electron microscopy (SEM). The dislocations found outside a buried-layer diffused area (emitter edge dislocations) propagate clearly into an overlying silicon epitaxial layer; this propagation is likely to take place along in the [112̄] direction.

Effects of diffusion-induced dislocations on the excess low-frequency noise

This paper discusses the device characteristics of the emitter-base junction, linearity of the static forward-current transfer ratio, and excess low-frequency noise in bipolar transistors by use of gate-controlled n-p-n transistors fabricated by varying the deposition rate of phosphosilicate glass in the emitter deposition. As a result of increasing the deposition rate of phosphosilicate glass, the following results were obtained. 1) Diffusion-induced dislocations and emitter edge dislocations extended from the emitter through the collector and their densities increased. 2) Diode reverse current of the emitter-base junction increased. 3) Linearity of the static forward-current transfer ratio was reduced at low current level. 4) Excess low-frequency noise increased.

Effect of non-uniform emitter current distribution on power transistor stability

The concentration of current to the edges of an emitter in a power transistor is known to be due to the transverse voltage drop along the emitter face caused by base current flow. The calculation of this ‘crowding’ phenomenon is usually made assuming an isothermal emitter surface. It is shown that in general, when a transistor is dissipating power, that the emitter current can crowd either to the center portion or edge of the emitter, depending on the value of operating collector voltage and current. The non-uniform current distribution results from a temperature peak at the center of the emitter causing a concentration of current to the emitter center; this is counteracted by the transverse base voltage drop causing crowding to the emitter edge. The effect of this non-uniform emitter current distribution on transistor thermal stability is investigated for two transistor designs—one simulating an alloy transistor and the other a diffused-base transistor. The results indicate that the wide-base alloy device is more stable for a given power level. Values of external emitter or base resistance necessary for thermal stabilization at high power levels are calculated for the two different transistor designs. In both cases for a given power level, stabilization is more easily achieved at high current, low collector voltage rather than low current, high voltage.

Influence of wafer thickness and carrier recombination on the cutoff frequency of alloy-junction transistors

The influence of wafer thickness and carrier recombination on the α-cutoff frequency of the “intrinsic” transistor is studied. First, M oyjes' solution of the diffusion of minority carriers in a symmetrical junction transistor is used to find the d.c. transport factor. This is then converted to the a.c. case and finally an implicit equation is found for the cutoff frequency as a function of wafer thickness θ and surface recombination velocity S. It is shown that, for S < 3000 cm/sec, the influence of surface recombination is negligible. At very narrow basewidths the current density is very high at the emitter edge and this decreases the diffusion length. More important seems to be the fact that the carriers' path (from slanted edge of emitter to slanted edge of collector) is longer than the geometrical basewidth. A reduction in wafer thickness decreases this effect and thus increases the cutoff frequency, in spite of increasing the current density at the emitter edge. The most important equations have been represented graphically for the particular case of the STC TK20 transistor.