Engineering Of Embedded Systems Research Articles

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

A Practical Application of ARM Cortex-M3 Processor Core in Embedded System Engineering

A Practical Application of ARM Cortex-M3 Processor Core in Embedded System Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Nowadays, multi-processor systems play a critical role in embedded system engineering. As a result, the generation of optimal concurrent implementations is an unavoidable but difficult task. Correct concurrent codes achieving maximum performance on the target platform are hard to obtain. On the one hand, dependencies on concurrent computations, such as shared variables or synchronizations, are extremely difficult to analyze from source code. On the other hand, it is completely unfeasible for designers to manually generate multiple implementations in order to evaluate and compare all the possible design alternatives. To overcome these limitations, this paper presents an automatic code generation approach focusing on communication channel semantics. The approach proposes the use of UML/MARTE models to enable designers to graphically handle dependencies and concurrency of the models. As a result, the automatic generation process enables multiple design alternatives to be easily obtained and evaluated without adding manual effort to the design process. To demonstrate these capabilities, the methodology is tested with two large examples.

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Editor's Message to Special Issue of Embedded Systems Engineering

Real-time distributed simulations in an HLA framework: Application to aircraft simulation

This paper presents some ongoing research carried out in the context of the PRISE Project (Research Platform for Embedded Systems Engineering). This platform has been designed to evaluate and validate new embedded system concepts and techniques through a special hardware and software environment. Since much actual embedded equipment is not available, corresponding behavior is simulated within a high-level architecture (HLA) federation implemented with a run-time infrastructure (RTI) called CERTI and developed at ONERA. HLA is currently largely used in many simulation applications, but the limited performances of the RTIs raise doubts over the feasibility of HLA federations with real-time requirements. This paper addresses the problem of achieving real-time performances with the HLA standard. Several experiments are discussed using well-known aircraft simulators such as Microsoft Flight Simulator, FlightGear, and X-plane connected with the CERTI RTI. The added value of these activities is to demonstrate that according to a set of innovative solutions, HLA architecture is well suited to achieve hard real-time constraints. Finally, a formal model guaranteeing the schedulability of concurrent processes is also proposed.

Editor^|^apos;s Message to Special Issue on Embedded Systems Engineering

Editor^|^apos;s Message to Special Issue on Embedded Systems Engineering

Editor^|^apos;s Message to Special Issue on Embedded Systems Engineering

Editor^|^apos;s Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering

Editor's Message to Special Issue on Embedded Systems Engineering