Design Process Of Embedded Systems Research Articles

A Survey on Performance Optimization of High-Level Synthesis Tools

Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

Automotive Electronics:Enhancing the Learning through Integrated Laboratory

Present days' automotive embedded systems have become multifaceted in nature, and their performance has been enabled by introduction of electronics at all levels of design and manufacturing. The purpose of introducing a course on automotive electronics at under graduate level for the electrical sciences stream was to address the needs of embedded and automotive industries and hence providing the necessary knowledge and skills required for those industries. This paper discusses the process of mixing cognitive and performance learning objectives into one course; which is realized by integrating laboratory with the theory. The laboratory had a focus of building automotive electronics development and test environment for three main domains of automotive which includes power train, comfort/safety and In-vehicle networking. The paper also discusses about the development of in house experimental trainer modules which demonstrate the entire working of engine management systems. The laboratory had four different levels of experiments which enabled the students to experience typical automotive embedded system design process. At the same time it is observed that all the levels also address the major three domains of automotive as mentioned earlier. The level one included experiments belonging to automotive sub-systems, demonstration of cut-away modules, level two included model based simulation experiments using MATLAB/SIMULINK C the last level four was realized through system integration an extended activity which included the integration of sub-modules developed in earlier levels. The integration of laboratory to the theory course enabled to achieve both technical and professional outcomes of ABET[1]. The outcomes b, c, d, g, i, j, and k were achieved. The paper presents the details of attainment of these outcomes.

A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors

During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during the design, so that the search process for finding the optimal system configurations will be rapid and more efficient. The Bayesian belief network (BBN)-based modeling framework for design space pruning proposed in this paper attempts to resolve the existing limitation in imparting domain knowledge and provides a pioneering effort to support the designer during the process of application specific system design. The Xtensa customizable processor architecture from Tensilica and a very long instruction word (VLIW) processor architecture are considered as example target platforms to impart the domain knowledge for the proposed model. Case studies in support of the proposed model are presented in order to understand how BBN can be used for design space pruning by propagating the evidence and arriving at probabilistic inferences to ease the decision-making process. The results show that the design space reduces drastically from a few million design options available to just less than one hundred for Xtensa architecture and from a few billions of design options available to just few thousands for VLIW architecture. The work also validates the pruned design points for their optimality.

Assignment of unexpected tasks in embedded system design process

Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer.

Improving the efficiency of functional verification based on test prioritization

Functional verification has become the key bottleneck that delays time-to-market during the embedded system design process. And simulation-based verification is the mainstream practice in functional verification due to its flexibility and scalability. In practice, the success of the simulation-based verification highly depends on the quality of functional tests in use which is usually evaluated by coverage metrics. Since test prioritization can provide a way to simulate the more important tests which can improve the coverage metrics evidently earlier, we propose a test prioritization approach based on the clustering algorithm to obtain a high coverage level earlier in the simulation process. The k-means algorithm, which is one of the most popular clustering algorithms and usually used for the test prioritization, has some shortcomings which have an effect on the effectiveness of test prioritization. Thus we propose three enhanced k-means algorithms to overcome these shortcomings and improve the effectiveness of the test prioritization. Then the functional tests in the simulation environment can be ordered with the test prioritization based on the enhanced k-means algorithms. Finally, the more important tests, which can improve the coverage metrics evidently, can be selected and simulated early within the limited simulation time. Experimental results show that the enhanced k-means algorithms are more accurate and efficient than the standard k-means algorithm for the test prioritization, especially the third enhanced k-means algorithm. In comparison with simulating all the tests randomly, the more important tests, which are selected with the test prioritization based on the third enhanced k-means algorithm, achieve almost the same coverage metrics in a shorter time, which achieves a 90% simulation time saving.

Assignment of unexpected tasks in embedded system design process

Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer.

Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems

Temperature and power are two major issues for multiple supply voltage (MSV)-aware embedded systems that due to their different physical behavior are required to be considered together in the system design especially in applications with hard real-time constraints. In such applications critical path characteristics of a task graph play a key role in finding an MSV-aware floorplan that attempts to optimize temperature and power simultaneously. In this paper, we propose a multi-objective optimization framework to find an MSV-aware floorplan that satisfies these objectives simultaneously in the embedded system design process. This framework is based on integer linear programming (ILP) formulation which is further enhanced with a simulated annealing technique to reduce the complexity of the problem and thus execution time of it. As a trade-off between accuracy and execution time, a heuristic algorithm is also presented for scenarios with rather large design space where finding the optimal solution or Pareto optimal set is a formidable task and time consuming. The experimental results show that the proposed framework suggests floorplans that are more power-efficient compared to the cases that only attempt to optimize the temperature and attains lower temperature compared to the cases that only optimize the power. These results confirm the effectiveness of the proposed approach. Moreover, an interesting and counter-intuitive finding is that by increasing the supply voltage magnitude of the MSV-chip the total power and peak temperature not only do not increase but also decrease in some scenarios. This is due to the impacts of the critical paths of the application graph.

Design and Realization of Simulation Environment of Embedded Software and Hardware Intergration Based on GEF

Embedded software and hardware integration simulation platform is developed for simulating the embedded systems design process in current engineering system, which can facilitate finding various problems in system design process. For example, in the system scheme phase, the scheme and design verification are untimely and inadequate. In the early prototype phase, software development lags behind result in deferral of the overall progress of the system. And in the late prototype stage, the problem is lacking configuration item test environment. Embedded software and hardware integration simulation platform can provide verification of hardware and software integration and test development environment. Therefore, the quality of software development in embedded systems can be significantly improved and development cycle can be remarkably shortened by using this simulation platform.

32-Bit NxN Matrix Multiplication: Performance Evaluation for Altera FPGA, i5 Clarkdale and Atom Pineview-D Intel General Purpose Processors

Nowadays mobile devices represent a significant portion of the market for embedded systems, and are continuously demanded in daily life. From the end-user perspective size, weight, features are the key quality criteria. These benchmarks criteria became the usual design constraints in the embedded systems design process and put a high impact on the power consumption. This paper survey and explore different low power design techniques for FPGA and processors. We compare, evaluate, and analyze, the power and energy consumption in three different designs namely, Altera FPGA Cyclone II which has a systolic array matrix multiplication implemented, i5 Clarkdale, and Atom Pineview-D Intel general purpose processors, which multiply two nxn 32-bit matrices and produce a 64-bit matrix as an output. We concluded that FPGA is a more power and energy efficient on low matrix size. However, general purpose processor performance is close to FPGA on larger matrix size as the larger cache size in general purpose processor help in reducing latency. We also concluded that the performance of FPGA can be improved in terms of latency if more systolic array processing elements are implemented in parallel to allow more concurrency.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

On the Utilization of Java Technology in Embedded Systems

Java technology has seen an impressive growth in popularity since its introduction in 1995. Although ithas foremost proved its usefulness in the Internet domain, powerful marketactors are currently moving Java into the embedded systems domain. In thisarticle we identify major design issues in embedded systems, and analyze thesuitability of Java technology in such systems. We find that Java technologycan contribute to the embedded system design process on a system level byfacilitating higher run-time reliability and the technology can simplify maintenanceof the product throughout its life cycle. In addition, programmer efficiencyand productivity may be improved, especially for web based applications anddistributed embedded systems.

Practical Linux programming: device drivers, embedded systems, and the Internet

From the Publisher: Linux is becoming the OS of choice for embedded system designers and engineers, due to itsreal-time power and flexibility. This book/CD package introduces the essentials of the device driver and embedded system design process, including network printers, data acquisition systems, entrance security systems, and other general applications. It also addresses the growing need to integrate the Internet into all aspects of the design process. This unique approach is covered through examples that teach programmers how to incorporate Internet-related Web and database technology seamlessly with Linux inter-process communication facilities. These key technologies are covered throughout the book with real-world tutorials that teach programmers how to develop their own embedded applications. KEY FEATURES - Integrates the Internet design issues of Web and database technologies with inter-process communication facilities - Shows how to modularize a design project into manageable objects to achieve a fast and efficient product development cycle - Includes detailed coverage of Perl and Shell programming, HTML tags, SQL queries, and GNU system tools - Companion CD-ROM includes source code for all project examples and valuable third party software Author Biography: Ashfaq A. Khan is a development engineer for Xerox Corp. with over 20 years of experience designing and implementing embedded systems. Khan has conducted several workshops on embedded system design and is an adjunct professor at the University of California, Irvine. He resides in Torrance, CA.