Abstract
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.
Highlights
There are two main orientations in embedded system research, the technological field and the methodological one [1]
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell
The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation
Summary
There are two main orientations in embedded system research, the technological field and the methodological one [1]. An automatic hardware/software partitioning methodology is proposed in order to develop the dynamically reconfigurable architecture. Design patterns [13] have been operated in order to develop reusable design tools in different engineering fields Many researches in this field are performed. Many researches are performed for the reusability problem in order to develop new design tools that encapsulate all co-design phases in order to implement intellectual property (IP) blocks. One attempt proposed in [20,21] have as aim to develop the smartcell design tools in order to implement HW and SW IP blocks for heterogeneous platforms This smartcell is developed with design pattern approach and oriented-object concept based on UML language. Our contribution to resolve the reusability problem consists in the synthesis of IP blocks for hardware and software solutions from direct acyclic graph (DAC). The conclusion and the future works are presented in the last section of this paper
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
