Embedded System Design Research Articles

Cognitive hierarchy thinking based behavioral game model for IoT power control algorithm

The Internet of Things (IoT) describes a future world of interconnected physical objects, with several applications in the areas of smart environments. To implement the IoT concept, the research in the areas of power controlled circuits, embedded systems design, network protocols and control theory should be required. With the much advancement in these areas, the realization of IoT is becoming increasingly probable. In this paper, we propose a novel adaptive power control scheme for IoT systems. Based on the cognitive hierarchy thinking mechanism, our proposed scheme is designed as a new behavioral game model to adaptively control the power level. To effectively solve the power control problem in IoT systems, game theory is well-suited and an effective tool. The experimental result illustrates that our game-based approach can get an effective transmission power, which can make the communication rate maximal. Under dynamic IoT system environments, it is highly desirable property.

Focus on test, measurement, and analytical equipment

Focus on test, measurement, and analytical equipment

An Efficient Technique of Application Mapping and Scheduling on Real-Time Multiprocessor Systems for Throughput Optimization

Multiprocessor systems are becoming ubiquitous in today’s embedded systems design. In this article, we address the problem of mapping an application represented by a Homogeneous Synchronous Dataflow (HSDF) graph onto a real-time multiprocessor platform with the objective of maximizing total throughput. We propose that the optimal solution to the problem is composed of three components: actor-to-processor mapping, retiming, and actor ordering on each processor. The entire problem is systematically modeled into a Boolean Satisfiability (SAT) problem such that the optimal solution can be guaranteed theoretically. In order to explore the vast solution space more efficiently, we develop a specific HSDF theory solver based on the special characteristics of the timed HSDF, and integrate it into the general search framework of the SAT solver. Two alternative integration methods based on branch-and-bound are presented to achieve early branch pruning in the search space; thus, the scalability is greatly improved. Extensive performance evaluation on synthetic examples and a case study on the realistic H.264 Video Decoder show that our approach provides as much as 76.9% throughput improvement, and is scalable to industry-sized applications.

Property preservation of refinement for Petri net based representation for embedded systems

Embedded systems have many applications in our life. Petri net based Representation for Embedded Systems (PRES+) is a promising methodology for modeling, verification, analysis and control of embedded systems. But the state space explosion problem is somewhat tedious for PRES+ to specify and analyze large complex embedded systems. To solve state space explosion problem of PRES+, in this work, we concern with a method for expanding PRES+ model to the desired level of detail using refinement. A kind of refinement approach for PRES+ is proposed. We propose definitions of two PRES+ models have the same dynamic properties, such as reachability, timing and functionality. Reachability, timing and functionality preservations of the refined net are investigated. Definitions of liveness and boundedness of PRES+ are presented. We propose conditions under which liveness and boundedness will be preserved by using this refinement approach. A temperature measure and control example illustrates the efficiency of our refinement approach on practical applications. These results can be applied nicely to solve embedded systems design problems.

ASTROLABE

Building abstract system-level models that faithfully capture performance and functional behavior for embedded systems design is challenging. Unlike functional aspects, performance details are rarely available during the early design phases, and no clear method is known to characterize them. Moreover, once such models are built, they are inherently complex as they mix software models, hardware constraints, and environment abstractions. Their analysis by using traditional performance evaluation methods is reaching the limit. In this article, we present a systematic approach for building stochastic abstract performance models using statistical inference and model calibration, and we propose statistical model checking as a scalable performance evaluation technique for them.

An Encyclopedia Coverage of Compiler’s, Programmer’s & Simulator’s for 8051, PIC, AVR, ARM, Arduino Embedded Technologies

<h2><span lang="EN-GB">In today’s world, everything from small needle to airplane engineering is surrounded by embedded systems. Embedded System technology not only lays foundation for development but is also acting as Backbone for mankind in almost in every area of science, engineering, research and daily living. The world of embedded systems is mainly surrounded by: Microcontrollers and Microprocessor’s. To work in the area of Embedded Systems design and development is both interesting and challenging- Interesting in the sense, as everything is getting intelligent, advanced and feature rich day by day and the embedded system’s field is progressing by leaps and bounds. But challenging in the way, that resources are very limited in terms of design and implementation. The most important crucial challenges nowadays in front of embedded system engineers are- <strong><span style="text-decoration: underline;">Which programmer to Use</span></strong>? <strong><span style="text-decoration: underline;">Which compiler to use for source code development</span></strong>? <strong><span style="text-decoration: underline;">Which simulator to use to simulate the overall behavior of system</span></strong>? As every compiler, programmer and simulator has distinct features, so selecting the best one as per one’s requirement has always remained a challenge. The main aim of this research paper is to overcome that difficulty by providing the researchers and embedded system engineers an encyclopedic platform of compilers, programmers and simulators for all sorts of embedded system technologies like 8051, PIC, ARM, AVR and Arduino so that choosing of the best platform in terms of compiler, programmer and simulator can become easy and time saving for everyone working in this area.</span></h2>

On applying multiple criteria decision analysis in embedded systems design

We focus here on the application of multi critera decision analysis (MCDA) techniques in hardware/software partitioning activities to be used in the design and deployment of embedded systems. Our goal is to identify the best existing methods and tools suitable to support the approach we have taken for the partitioning process. We provide this via a survey of the most well-known MCDA methods and tools (for a specific class of MCDA methods called multi attribute decision making. We identify a set of criteria that need to be addressed, in some way, by the methods, and implemented by related tools. These "11-suitability criteria" help us in deciding the appropriateness of the analysed methods and tools for the envisaged partitioning approach. In brief, we are interested that the MCDA methods are taking into account multiple extra-functional properties, expressed by a variety of types, with possible missing values, should enable dependency handling, decision traceability, etc. The conclusion is that there are criteria that are not fulfilled by any of the methods, and hence there is no method or tool that can directly used for the partitioning. However, the results shows the potential of using MCDA in the partitioning process and provide a good starting point for future research activities.

Controlling Petri Net Behavior using Priorities for Transitions

In this paper we examine how it is possible to control Petri net behavior with the help of transition priorities. Controlling here means forcing a process to behave in a stable way by ascribing priorities to transitions and hence transforming a classic Petri net into a Priority Petri net. For Petri net models stability is often ensured by liveness and boundedness. These properties are crucial in many application areas, e.g. workflow modeling, embedded systems design, and bioin- formatics. In this paper we study the problem of transforming a given live, but unbounded Petri net into a live and bounded one by adding priority constraints. We specify necessary conditions for the solvability of this problem and present an algorithm for ascribing priorities to net transitions in such a way that the resulting net becomes bounded while staying live.

A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors

During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during the design, so that the search process for finding the optimal system configurations will be rapid and more efficient. The Bayesian belief network (BBN)-based modeling framework for design space pruning proposed in this paper attempts to resolve the existing limitation in imparting domain knowledge and provides a pioneering effort to support the designer during the process of application specific system design. The Xtensa customizable processor architecture from Tensilica and a very long instruction word (VLIW) processor architecture are considered as example target platforms to impart the domain knowledge for the proposed model. Case studies in support of the proposed model are presented in order to understand how BBN can be used for design space pruning by propagating the evidence and arriving at probabilistic inferences to ease the decision-making process. The results show that the design space reduces drastically from a few million design options available to just less than one hundred for Xtensa architecture and from a few billions of design options available to just few thousands for VLIW architecture. The work also validates the pruned design points for their optimality.

Power-Aware Design Techniques of Secure Multimode Embedded Systems

Nowadays, embedded systems have been widely used in all types of application areas, some of which belong to the safety and reliability critical domains. The functional correctness and design robustness of the embedded systems involved in such domains are crucial for the safety of personal/enterprise property or even human lives. Thereby, a holistic design procedure that considers all the important design concerns is essential. In this article, we approach embedded systems design from an integral perspective. We consider not only the classic real-time and quality of service requirements, but also the emerging security and power efficiency demands. Modern embedded systems are not any more developed for a fixed purpose, but instead designed for undertaking various processing requests. This leads to the concept of multimode embedded systems, in which the number and nature of active tasks change during runtime. Under dynamic situations, providing high performance along with various design concerns becomes a really difficult problem. Therefore, we propose a novel power-aware secure embedded systems design framework that efficiently solves the problem of runtime quality optimization with security and power constraints. The efficiency of our proposed techniques are evaluated in extensive experiments.

A cost- and energy-efficient embedded system design based on instruction execution frequencies

In this paper, an embedded system that takes into account the frequency of the executed instructions to reduce memory space and save energy consumption is proposed. The object codes are split into the frequently executed instructions and the infrequently executed instructions (INFIs) by analyzing the trace files of applications. To reduce the use of memory space, the dictionary-based method is used to compress INFIs. To take into account energy consumption, the top-executed instructions are selected to encode as shorter codewords and wrapped into a pseudo instruction. When a pseudo instruction that contains several codewords is fetched, it can be decompressed to several continuous instructions to reduce the number of memory accesses. In addition, to further reduce energy consumption, a multiple reference table design is proposed to make a pseudo instruction contain more encoded codewords by shortening the length of an encoded instruction. From the simulation results, the proposed design that uses one 256-instruction reference table reduces the energy consumption about 50.4% compared to the dictionary-based method. In addition, to show the improvement of energy consumption for the proposed multiple reference table method over that using one reference table, we also show the simulation results of a design with two 256-instruction reference tables which shows less energy use than a design with one 512-instruction reference table by 12.1%.

Embedded System Design of a Maximum Power Point Tracking Controller for Traffic Light System Powered by Photovoltaic

Photovoltaic traffic light system is a significant application of renewable energy source. The develop the system use solar energy as an alternative effort of local authority to reduce expenditure for paying fees to power supplier which the power comes from conventional energy source. Since photovoltaic modules still have relatively low conversion efficiency, An alternative control of maximum power point tracking (MPPT) method applied to the traffic light system. MPPT is intended to catch up the maximum power at daytime in order to charge the battery at the maximum rate in which the power from the battery is intended to be used at night time or cloudy day. MPPT is actually a dc-dc converter that can step up or down of voltage in order to achieve the maximum power using Pulse Width Modulation (PWM) control. In this work, we design a MPPT using Microcontroller PIC16F877. Where this microcontroller will compare the voltage and current from PV system, and convert the new voltage and current to get maximum power output. Based on experiment, we obtained the voltage of operation use MPPT is at 16.454 V, this value had error 2.6%, if we compared with Maximum power point voltage of PV module that is 16.9V, based on this result then this MPPT control work successful to deliver the power from PV module to battery maximally.

Embedded System Design of Remote Healthcare Monitoring Center using Web-Technology

Healthcare must be as efficient as possible. Information and communication technologies (ICTs) have great potential to address some of the challenges faced by both developed and developing countries in providing accessible, cost-effective, high-quality healthcare services. Telemedical clinics use ICTs to overcome geographical barriers, and increase access to healthcare services. This is particularly beneficial for rural and underserved communities in developing countries – groups that traditionally suffer from lack of access to healthcare. This work proposes an Embedded system design using web-based technology to provide wide range of services in Telemedical clinics which facilitates the provision of medical aids from distance. So we implement Sensor nodes Circuit for collecting data and process them to extract useful body information. Sensors: are interfaced to microcontroller through analog module, the written software in the microcontroller processes data and the processing results are sent to the Laptop then to web-portal using Bluetooth connection and the flow chart of the written software is developed. The proposed System structure clarify 4 components (Medical Sensors, CCU Interface, Communication module, Application Platform). One of medical sensors is the temperature sensor, we used the temperature Resistance Equation to build the Algorithm to get the temperature measurements. We implement web-service using PHP-Programming and MySQL DataBase: To update and plot the response of sensors to the real world Remote Healthcare Monitoring center. An Experimental setup of Embedded system of sensors is tested. It is an effective solution for providing specialty healthcare in the form of improved internet-access and reduced cost to rural patients.

Assignment of unexpected tasks in embedded system design process

Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer.

Temperature-Constrained Feasibility Analysis for Multicore Scheduling

Multicore platforms are becoming the primary choice to achieve high performance in today’s embedded system design. However, under the current IC technology, the dramatic increase in power density has made the thermal issue a critical concern in design of multicore systems. In this paper, we study the problem on how to determine if a periodic dynamic voltage and frequency scaling (DVFS) schedule for a multicore platform is thermally feasible in satisfying a given peak temperature constraint. To solve this problem, we first develop a novel analytic method to quickly calculate the temperature at an arbitrary time instant, which can achieve orders-of-magnitude speedups over the HotSpot simulator. We then present an approach to pinpoint the peak temperature of a given periodic multicore DVFS schedule. Finally, we develop three methods to check the thermal feasibility of an arbitrary schedule. We formally prove the fundamental principles and validity of our proposed methods and use simulation results to demonstrate their effectiveness.

Guest Editorial: Special Issue on Cloud-Integrated Cyber-Physical Systems

The advances in wireless sensor devices, big data, mobile computing, and cloud computing offer tremendous opportunities to realize the seamless integration between the physical world and the cyber space. The cloud-integrated cyberphysical system (CCPS) refers to virtually representing physical system components, such as sensors, actuators, robots, and other devices in clouds, accessing (e.g., monitoring, actuating and navigating) those physical components through their virtual representations, and processing/managing/controlling the large amount of data collected from physical components in clouds in a scalable, real-time, efficient, and reliable manner. Particularly, integrating cloud computing techniques (e.g., virtualization, elastic re-configuration, and multi-tenancy of resources) with CPS techniques (e.g., real-time scheduling, adaptive resource management and control, and embedded system design) will bring hope to advance the state of the art, and allow previously unachievable systems such as cloud-integrated internet of vehicles to be built, deployed, managed, and controlled effectively. This Special Issue on CCPS solicits the manuscripts on rigorous research on theories, methodologies, tools, and testbeds for CCPS. In this special issue, we selected ten papers. Each paper was carefully reviewed by peer review and guest editors. In the following, we will overview the accepted papers that reflect recent advances.

A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators

Security and safety are more and more important in embedded system design. A key issue, hence lies in the ability of systems to respond safely when errors occur at runtime, to prevent unacceptable behaviors that can lead to failures or sensitive data leakage. In this paper, we propose a design approach that automatically generates on-chip monitors (OCMs) during high-level synthesis (HLS) of hardware accelerators (HWaccs). OCM checks at runtime the input/output timing behavior, the control flow execution and algorithmic properties (via American National Standards Institute C assertions) of the monitored HWacc. OCM is implemented separately from the HWacc and an original technique is introduced for their synchronization. Two synthesis options are proposed to tradeoff between performance and area. Experiment results show that error detection on the control flow is $16\times $ better compared to the existing approaches while the cost of assertions is reduced by 17.48% on average. The impact on execution time (i.e., latency of the HWacc) is decreased by $2.76\times $ at no area penalty and up to $4.5\times $ with less than 10% extra-area. The clock period overhead is at worst less than 5% and the overhead on the synthesis time of the HWacc to generate OCMs is 7.44% on average.

Two-steps into energy consumption optimisation due to the mapping of multimedia application to network on chip architecture

Energy-efficiency is becoming one of the most critical issues in embedded system design that target the multimedia application caused by the increasing number of intellectual property IP cores in network on chip NoC. This paper addresses the optimisation of NoC performances in term of power and latency, we proposed an optimisation technique that is an hybrid based-scheduling algorithm that evolve the cellular automata CA with genetic algorithm to solve mapping and scheduling problems where we mixed between GA easiest implementation and achievability of near global optimum solutions with CA simplicity and rigorous mathematical model to achieve our goal. In our algorithm, each transition rule represents a chromosome allowing an automatically programming of the transition rules of the evolutionary cellular automata. Also we have presented new dynamic voltage and frequency scaling technique that automatically detect the voltage change point in order to save power while respecting the timing constraints of the soft real-time multimedia application.

Two-steps into energy consumption optimisation due to the mapping of multimedia application to network on chip architecture

Energy-efficiency is becoming one of the most critical issues in embedded system design that target the multimedia application caused by the increasing number of intellectual property (IP) cores in network on chip (NoC). This paper addresses the optimisation of NoC performances in term of power and latency, we proposed an optimisation technique that is an hybrid based-scheduling algorithm that evolve the cellular automata (CA) with genetic algorithm to solve mapping and scheduling problems where we mixed between GA easiest implementation and achievability of near global optimum solutions with CA simplicity and rigorous mathematical model to achieve our goal. In our algorithm, each transition rule represents a chromosome allowing an automatically programming of the transition rules of the evolutionary cellular automata. Also we have presented new dynamic voltage and frequency scaling technique that automatically detect the voltage change point in order to save power while respecting the timing constraints of the soft real-time multimedia application.

Introduction to the special issue on reconfigurable cyber-physical and embedded system design

Introduction to the special issue on reconfigurable cyber-physical and embedded system design