Embedded Field Programmable Gate Array Research Articles

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called “FABulous” was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

Dual-resonant scanning multiphoton microscope with ultrasound lens and resonant mirror for rapid volumetric imaging

A dual-resonant scanning multiphoton (DRSM) microscope incorporating a tunable acoustic gradient index of refraction lens with a resonant mirror is developed for high-speed volumetric imaging. In the proposed microscope, the pulse train signal of a femtosecond laser is used to trigger an embedded field programmable gate array to sample the multiphoton excited fluorescence signal at the rate of one pixel per laser pulse. It is shown that a frame rate of around 8000 Hz can be obtained in the x–z plane for an image region with a size of 256 × 80 pixels. Moreover, a volumetric imaging rate of over 30 Hz can be obtained for a large image volume of 343 × 343 × 120 μm3 with an image size of 256 × 256 × 80 voxels. Moreover, a volumetric imaging rate of over 30 Hz can be obtained for a large image volume of 256 × 256 × 80 voxels, which represents 343 × 343 × 120 μm3 in field-of-view. The rapid volumetric imaging rate eliminates the aliasing effect for observed temporal frequencies lower than 15 Hz. The practical feasibility of the DRSM microscope is demonstrated by observing the mushroom bodies of a drosophila brain and performing 3D dynamic observations of moving 10-μm fluorescent beads.

Development of apparatus for mean-lifetime measurement of cosmic-ray muons using plastic scintillation detectors and FLASH-ADC/FPGA-based readout electronics

Introduction: This paper presents the development and results of an apparatus for measuring the mean lifetime of cosmic-ray muons. Methods: The apparatus uses three plastic scintillation detectors and a readout electronics system based on Flash Analog Digital Converter (Flash-ADC) and Embedded Field Programmable Gate Array (FPGA). The readout system has 8-bit resolution and a 125 Msample/sec sampling rate. The system's trigger and data collection are controlled through a computer interface based on LabVIEWTM. The readout electronics are calibrated with an accuracy of 8 nsec/TDC channel. Results: Over 6000 events were recorded during the measurements performed at ground level using aluminum as the muon stopping material, and the muon decay time spectrum was obtained and fit with a combination of two exponential components and a constant background. The mean lifetimes of negative and positive muons were determined. Conclusion: Our results indicate that the mean lifetimes of negative and positive muons in aluminum are 0.70 ± 0.24 µsec and 2.05 ± 0.16 µsec, respectively.

Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking

Both modern datacenter and embedded Field Programmable Gate Arrays (FPGAs) provide great opportunities for high-performance and high-energy-efficiency computing. With the growing public availability of FPGAs from major cloud service providers such as AWS, Alibaba, and Nimbix, as well as uniform hardware accelerator development tools (such as Xilinx Vitis and Intel oneAPI) for software programmers, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS).The major goal of this article is to figure out how to efficiently access the memory system of modern datacenter and embedded FPGAs in HLS-based accelerator designs. This is especially important for memory-bound applications; for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including (1) the clock frequency of the accelerator design, (2) the number of concurrent memory access ports, (3) the data width of each port, (4) the maximum burst access length for each port, and (5) the size of consecutive data accesses. Then, we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the memory systems of datacenter FPGAs (Xilinx Alveo U200 and U280) and embedded FPGA (Xilinx ZCU104) when changing those affecting factors, and we provide insights into efficient memory access in HLS-based accelerator designs. Comparing between the typically used soft and hardened memory systems, respectively, found on datacenter and embedded FPGAs, we further summarize their unique features and discuss the effective approaches to leverage these systems. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms on datacenter FPGAs with a soft (and thus more flexible) memory system. Compared to the baseline designs, optimized designs leveraging our insights achieve about\( 3.5\times \)and\( 8.5\times \)speedups for the KNN and SpMV accelerators. Our final optimized KNN and SpMV designs on a Xilinx Alveo U200 FPGA fully utilize its off-chip memory bandwidth, and achieve about\( 5.6\times \)and\( 3.4\times \)speedups over the 24-core CPU implementations.

Hardware-Accelerated Real-Time Spectrum Analyzer With a Broadband Fast Sweep Feature Based on the Cost-Effective SDR Platform

Radio Frequency (RF) spectrum monitoring and broadband signal analysis have multiple application areas, especially in the era of a constantly growing number of wireless devices. One of the essential challenges for a spectrum sensor is to achieve an adequate measurement rate over a wide bandwidth to detect signals of short duration so that a low latency response can be provided. In procedures that require field measurements, and some compromise in accuracy is acceptable, low-cost Software Defined Radio (SDR) devices can be used instead of expensive and bulky professional spectrum analyzers. This paper introduces a real-time swept spectrum sensor based on LimeSDR-USB with custom embedded Field Programmable Gate Array (FPGA) firmware, designed to outperform similar software implementations. The Welch’s spectral density estimation is implemented in hardware to minimise the USB transfer rate and offload the host PC signal processing. Furthermore, the frequency tuning state machine and cache calibration memory are also managed by the FPGA to reduce the blind time during broadband sweep. The performance of the proposed solution indicates up to 96 MHz of real-time bandwidth along with a capability of less than millisecond cumulative sweep time per gigahertz. The characteristics of various design elements are investigated and refined during simulation and laboratory measurements, whereas the final prototype implementation is verified in real-world scenarios. The results demonstrate the effectiveness of the proposed device as a sensor for propagation studies, multiband spectrum utilisation monitoring, and spectral white spaces detection.

Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework.

FARD

In the last few years Internet of Things (IoT) applications are moving from the cloud-sensor paradigm to a more variegated structure where IoT nodes interact with an intermediate fog computing layer. To enable compute-intensive tasks to be executed near the source of the data, fog computing nodes should provide enough performance and be sufficiently energy efficient to run on the field. Within this context, embedded Field Programmable Gate Array (FPGA) can be used to improve the performance per Watt ratio of fog computing nodes. In this paper we present Fog Acceleration through Reconigurable Devices (FARD), a distributed system that exploits FPGAs to accelerate compute-intensive tasks in fog computing applications. FARD is able to efficiently run distributed fog applications thanks to a well-defined application structure, a per-application isolated network overlay and thanks to the acceleration of tasks. Results show energy efficiency improvements while efficiently enabling cooperation across fog nodes.

A review on embedded field programmable gate array architectures and configuration tools

Nowadays, systems-on-chip have reached a level where nonrecurring engineering costs have become a great challenge due to the increase of design complexity and postfabrication errors. Embedded field programmable gate arrays (eFPGAs) represent a viable alternative to overcome these issues since they provide postmanufacturing flexibility that can reduce the number of chip redesigns and amortize chip fabrication cost. In this paper, we present an overview on eFPGAs and their architectures, computer aided design (CAD) tools, and design challenges. An eFPGA must be well-designed and accompanied by an optimized CAD tool suite to respond to target application's requirements in terms of power consumption, area, and performance. In this survey, we studied coarse-grained eFPGAs with customized blocks which are used for domain-specific applications and fine-grained eFPGAs that are used for general purposes but have lower performance.

A Design Methodology of Digital Control System for MEMS Gyroscope Based on Multi-Objective Parameter Optimization.

This paper presents a novel multi-objective parameter optimization method based on the genetic algorithm (GA) and adaptive moment estimation (Adam) algorithm for the design of a closed-loop control system for the sense mode of a Microelectromechanical systems (MEMS) gyroscope. The proposed method can improve the immunity of the control system to fabrication tolerances and external noise. The design procedure starts by deriving a parameterized model of the closed-loop of the sense mode. The loop parameters are then optimized by the GA. Finally, the ensemble of optimized loop parameters is tested by Monte Carlo analysis to obtain a robust optimal solution. Simultaneously, the Adam-least mean square (LMS) demodulator, which is appropriate for the demodulation of very noisy signals, is also presented. Compared with the traditional method, the time consumption of the design process is reduced significantly. The digital control system is implemented by the print circuit board based on embedded Field Programmable Gate Array (FPGA). The experimental results show that the optimized control loop has achieved a better performance, the system bandwidth in open-loop and optimal closed-loop control system is about 23 Hz and 101 Hz, respectively. Compared to a non-optimized closed-loop system, the bias instability reduced from 0.0015°/s to 7.52 × 10−4°/s, the scale factor increased from 17.7 mV/(°/s) to 23 mV/(°/s) and the non-linearity of the scale factor reduced from 0.008452% to 0.006156%.

A Parallel Image Registration Algorithm Based on a Lattice Boltzmann Model

Image registration is a key pre-procedure for high level image processing. However, taking into consideration the complexity and accuracy of the algorithm, the image registration algorithm always has high time complexity. To speed up the registration algorithm, parallel computation is a relevant strategy. Parallelizing the algorithm by implementing Lattice Boltzmann method (LBM) seems a good candidate. In consequence, this paper proposes a novel parallel LBM based model (LB model) for image registration. The main idea of our method consists in simulating the convection diffusion equation through a LB model with an ad hoc collision term. By applying our method on computed tomography angiography images (CTA images), Magnet Resonance images (MR images), natural scene image and artificial images, our model proves to be faster than classical methods and achieves accurate registration. In the continuity of 2D image registration model, the LB model is extended to 3D volume registration providing excellent results in domain such as medical imaging. Our method can run on massively parallel architectures, ranging from embedded field programmable gate arrays (FPGAs) and digital signal processors (DSPs) up to graphics processing units (GPUs).

Design and Implementation of a New Wireless Carotid Neckband Doppler System with Wearable Ultrasound Sensors: Preliminary Results

Noninvasive monitoring of blood flow in the carotid artery is important for evaluating not only cerebrovascular but also cardiovascular diseases. In this paper, a wireless neckband ultrasound Doppler system, in which two 2.5-MHz ultrasonic sensors are utilized for acquiring Doppler signals from both carotid arteries, is presented for continuously evaluating blood flow dynamics. In the developed wireless neckband Doppler system, the acquired Doppler signals are quantized by 14-bit analog-to-digital-converters running at 40 MHz, and pre-processing operations (i.e., demodulation and clutter filtering) are performed in an embedded field programmable gate array chip. Then, these data are transferred to an external smartphone (i.e., Galaxy S7, Samsung Electronics Co., Suwon, Korea) via Bluetooth 2.0. Post-processing (i.e., Fourier transform and image processing) is performed using an embedded application processor in the smartphone. The developed carotid neckband Doppler system was evaluated with phantom and in vivo studies. In a phantom study, the neckband Doppler system showed comparable results with a commercial ultrasound machine in terms of peak systolic velocity and resistive index, i.e., 131.49 ± 3.97 and 0.75 ± 0.02 vs. 131.89 ± 2.06 and 0.74 ± 0.02, respectively. In addition, in the in vivo study, the neckband Doppler system successfully demonstrated its capability to continuously evaluate hemodynamics in both common carotid arteries. These results indicate that the developed wireless neckband Doppler system can be used for continuous monitoring of blood flow dynamics in the common carotid arteries in point-of-care settings.

Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis

Embedded field programmable gate arrays (eFPGA) can provide modern systems-on-a-chip (SoCs) with the flexibility required to face the growth of nonrecurring engineering and manufacturing costs. On the other hand, SoC designers usually perceive eFPGAs as area-hungry IPs with poor flexibility in terms of performance, power and area tradeoff since they are typically available as custom-designed hard macros. In this scenario, technology scaling is allowing designers to reduce the impact of the eFPGA area gap, while effective exploitation of all the technology options (e.g., the transistor threshold) entails moving toward soft-core eFPGAs to match specific application needs. In this paper, we propose an look-up table-based soft-core eFPGA featuring a synthesizable and parametric architecture. A key point of our proposal is that we have adopted a multistage switching network (MSSN) to implement the programmable interconnect, since this ensures a synthesizable and congestion-free architecture. Quantitative evaluation of our eFPGA shows a significantly wide design-space available on very different technologies (we experimented STMicroelectronics CMOS 65 nm and BCD9s 0.11 $\mu \text{m}$ ). Application-driven evaluation showed how for a fixed eFPGA size (i.e., number of logic blocks) different configurations of the MSSN allow designers to speed up performance by 20/60%, as well as to maximize the computational density for a given area budget.

A Control System and Streaming DAQ Platform with Image-Based Trigger for X-ray Imaging

High-speed X-ray imaging applications play a crucial role for non-destructive investigations of the dynamics in material science and biology. On-line data analysis is necessary for quality assurance and data-driven feedback, leading to a more efficent use of a beam time and increased data quality. In this article we present a smart camera platform with embedded Field Programmable Gate Array (FPGA) processing that is able to stream and process data continuously in real-time. The setup consists of a Complementary Metal-Oxide-Semiconductor (CMOS) sensor, an FPGA readout card, and a readout computer. It is seamlessly integrated in a new custom experiment control system called Concert that provides a more efficient way of operating a beamline by integrating device control, experiment process control, and data analysis. The potential of the embedded processing is demonstrated by implementing an image-based trigger. It records the temporal evolution of physical events with increased speed while maintaining the full field of view. The complete data acquisition system, with Concert and the smart camera platform was successfully integrated and used for fast X-ray imaging experiments at KIT’s synchrotron radiation facility ANKA.

Real-Time Processing System for the JET Hard X-Ray and Gamma-Ray Profile Monitor Enhancement

The Joint European Torus (JET) is currently undertaking an enhancement program, in which one of the objectives is to test relevant diagnostics for the International Thermonuclear Experimental Reactor (ITER), the reference for the next generation of fusion experiments. One of the challenges in ITER is the provision of real-time data analysis and compression capabilities, to sustain the expected long duration discharges and the high acquisition rates achieved by recent data acquisition systems. Foreseeing this real-time requirement, a new system was developed and installed at JET for the gamma-ray and hard X-ray profile monitor diagnostic. The new system, which is connected to 19 CsI(Tl) photodiodes in order to obtain the line-integrated profiles of the gamma-ray and hard X-ray emissions, was designed to overcome the data acquisition limitations of the present fast electron Bremsstrahlung diagnostic (FEB), while exploiting the required real-time features. This paper presents the real-time processing architecture for the JET gamma-ray and hard X-ray profile monitor. The system hardware, based on the Advanced Telecommunication Computer Architecture (ATCA) standard, includes reconfigurable digitizer modules with embedded Field Programmable Gate Array (FPGA) devices capable of acquiring and simultaneously processing data in real-time from the 19 detectors. A suitable algorithm was developed and implemented in the FPGAs, which are able to deliver the corresponding energy of the acquired pulses, and its associated occurrence time. The real-time processed data is sent periodically, during the discharge, through the JET real-time Asynchronous Transfer Mode (ATM) network, and stored in the JET scientific databases at the end of the pulse. Publishing the processed data in the ATM network enables it to be used for machine control purposes (e.g. the information about the line-integrated emissions of the hard X-rays in real time can be used to determine the lower hybrid current drive deposition before the main heating phase). Additionally, the real-time processed data is used for local calibration, using embedded radioactive sources to build in real-time the 19 channels spectra. The acquired raw data is also stored in the digitizer modules' local memory and retrieved after the pulse to the JET database, where it can be post-processed offline to validate the real-time algorithms. The interface between the ATCA digitizers, the JET Control and Data Acquisition System (CODAS) and the JET real-time network is provided by the Multithreaded Application Real-Time executor (MARTe). From the experimental results it was concluded that it is possible to measure in real-time the line-integrals of both hard X-ray and gamma-ray emissions, covering energy range from ∼200 keV to 8 MeV. This allows us to meet two of the major milestones: the ability to process and supply high volume data rates in real-time over a wide spectrum energy range.

Precision Control of Modular Robot Manipulators: The VDC Approach With Embedded FPGA

A systematic solution to precision control of modular robot manipulators without using joint torque sensing is presented in this paper for the first time. Using the virtual decomposition control (VDC) approach with embedded field programmable gate array (FPGA) logic devices, the proposed solution solves a long-standing problem of lacking control precision fundamentally associated with the modular robot manipulators. As a result, this solution allows modular robot manipulators to possess not only their traditional advantages (such as reconfigurability, flexibility, versatility, and ease of use) but precision control capability as well. A hierarchical master-slave control structure is used, which is supported by a high-speed communication system modified from SpaceWire (IEEE 1355), transferring a limited amount of data between the master and slave nodes at a rate of 1000 Hz. In each module, the FPGA logic implementation uses multiple sampling periods of 163.8 μs, 1.28 μs, and 20 ns. A gravity counterbalance spring provides a design option for the purpose of energy saving. Experimental results demonstrate unprecedented control precision, which is attributed to the use of both the VDC approach and embedded FPGA implementation. The ratio of the maximum position tracking error to the maximum velocity reaches 0.00012 s-more than an order of magnitude better than available technologies in control of robots with harmonic drives. The solution presented in this paper is also applicable to integrated robot manipulators using embedded FPGA controllers.

Real-time algorithms for JET hard X-ray and gamma-ray profile monitor

The steady state operation with high energy content foreseen for future generation of fusion devices will necessarily demand dedicated real-time tools and mechanisms for data handling and machine control. Consequently, the real-time systems for those devices should be carefully selected and their capabilities previously established. The Joint European Torus (JET) is undertaking an enhancement program, which includes tests of relevant real-time tools for the International Thermonuclear Experimental Reactor (ITER), a key experiment for future fusion devices. In these enhancements a new Data AcQuisition (DAQ) system is included, with real-time processing capabilities, for the JET hard X-ray and gamma-ray profile monitor. The DAQ system is composed of dedicated digitizer modules with embedded Field Programmable Gate Array (FPGA) devices. The interface between the DAQ system, the JET control and data acquisition system and the JET real-time data network is provided by the Multithreaded Application Real-Time executor (MARTe). This paper describes the real-time algorithms, developed for both digitizers’ FPGAs and MARTe application, capable of meeting the DAQ real-time requirements. The new DAQ system, including the embedded real-time features, was commissioned during the 2012 experiments. Results achieved with these real-time algorithms during experiments are presented.

Cosmic ray angular distribution employing plastic scintillation detectors and flash-ADC/FPGA-based readout systems

Abstract It is known that secondary cosmic rays are high energetic particles which are products of shower particles, when primary cosmic rays from outer space hit the atmosphere molecules. Many studies of cosmic rays show that cosmic flux depends on the depth of atmosphere. At ground level, most secondary cosmic rays are muons, a type of charged particle, and have angular dependence. The purpose of this article was to develop the telescope with two plastic scintillation detectors to investigate the angular distribution of cosmic rays at ground level. Directions of investigation were carried out vertical, 45-degree oblique and horizontal directions with respect to earth surface, approximately from North to South. Electronic readout system was developed from Flash Analog Digital Converter (Flash-ADC) of 8 bits-250Ms/sec, and Embedded Field Programmable Gate Array (FPGA)-based trigger. LabVIEWTM interface was written for controlling trigger system and taking data. For each direction measurement, the deposited energy spectra in the scintillators were obtained. The interest of cosmic-ray events was analyzed for counting. Angular distribution was obtained quantitatively. The experiment has been done at University of Science-HCMC.

A heterodyne interferometer with periodic nonlinearities smaller than ±10 pm

The PTB developed a new optical heterodyne interferometer in the context of the European joint research project ‘Nanotrace’. A new optical concept using plane-parallel plates and spatially separated input beams to minimize the periodic nonlinearities was realized. Furthermore, the interferometer has the resolution of a double-path interferometer, compensates for possible angle variations between the mirrors and the interferometer optics and offers a minimal path difference between the reference and the measurement arm. Additionally, a new heterodyne phase evaluation based on an analogue to digital converter board with embedded field programmable gate arrays was developed, providing a high-resolving capability in the single-digit picometre range. The nonlinearities were characterized by a comparison with an x-ray interferometer, over a measurement range of 2.2 periods of the optical interferometer. Assuming an error-free x-ray interferometer, the nonlinearities are considered to be the deviation of the measured displacement from a best-fit line. For the proposed interferometer, nonlinearities smaller than ±10 pm were observed without any quadrature fringe correction.

Phase measurement of various commercial heterodyne He–Ne-laser interferometers with stability in the picometer regime

In order to be able to resolve displacements of a picometer with widely used commercially available heterodyne interferometers, an advanced phase meter was developed at PTB. Key to this level of accuracy is the use of a state-of-the-art analogue-to-digital converter (ADC) board enabling the implementation of a phase-evaluation method by using embedded field programmable gate arrays. Experimental results obtained with commercially available heterodyne laser interferometer components prove that the proposed phase-evaluation procedure is capable of interpolating an optical fringe down into the picometer regime. The phase evaluation was moreover extended to track simultaneously two heterodyne beat frequencies with only two photodetectors and ADCs. Potential limitations of the long-term stability of heterodyne interferometers are discussed. The phase meter was tested, has been readily applied, can be easily adapted and is therefore to be used in a wide field of applications.

Configurable Embedded CPG-Based Control for Robot Locomotion

Recently, the development of intelligent robots has benefited from a deeper understanding of the biomechanics and neurology of biological systems. Researchers have proposed the concept of Central Pattern Generators (CPGs) as a mechanism for generating an efficient control strategy for legged robots based on biological locomotion principles. Although many studies have aimed to develop robust legged locomotion controllers, relatively few of them have focused on adopting the technology for fully practical embedded hardware implementations. In this contribution, a reconfigurable hardware implementation of a CPG-based controller which is able to generate several gaits for quadruped and hexapod robots is presented. The proposed implementation is modular and configurable in order to scale up to legged robots with different degrees of freedom. Experimental results for embedded Field Programmable Gate Array (FPGA) implementations for quadruped and hexapod robot controllers are presented and analysed.