Embedded Compression Research Articles

A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications

The memory bandwidth has become a design bottleneck in a video coding system, especially for high-end display resolutions. Embedded compression (EC) can efficiently save the memory bandwidth between a video coding system and its frame memory. If the memory bandwidth is reduced, its memory access power can also be saved. The tremendous memory bandwidth exhibits a serious design challenge on the throughput of an EC engine. In this study, a hardware-efficient EC algorithm and architecture is proposed. It comprises three core techniques: adaptive weighting-average prediction (AWP), fraction embedding method (FEM), and partition-based binary coding (PBC). AWP can switch prediction weightings according to surrounding texture condition, producing the residuals of an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8 \times 8$ </tex-math></inline-formula> block. The residual consists of an integer part and a fraction part (FP). FEM can smartly embed the FP into its sign bit, improving coding efficiency. PBC adaptively partitions the residuals into groups without complex filtering and converts them to efficient codewords. This study has a competitive compression ratio (CR) of 2.39, resulting in a memory bandwidth saving by 58%. Its hardware architecture is realized in TSMC CMOS 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology, presenting smooth data scheduling and regular data paths. The throughputs of both encoding and decoding can reach 12.8 Gpixels/s. Compared with other lossless EC codecs, this study can demonstrate better overall performance of CR, energy utilization, and area organization.

Algorithm and VLSI Architecture Designs of a Lossless Embedded Compression Encoder for HD Video Coding Systems

The demand for visual quality has been advanced by high display resolutions and frame rates. Nevertheless, these two issues have caused tremendous memory bandwidth in a video coding system. In this study, an efficient lossless embedded compression (EC) algorithm is proposed to save memory bandwidth, while keeping visual quality. The proposed lossless EC algorithm incorporates three core techniques: tree partition, half-pixel prediction and group-based binary coding. Tree partition classifies a [Formula: see text] block into Trunk, Branch and Leaf. With tree partition, half-pixel prediction produces individual residues for Trunk, Branch and Leaf. Group-based binary coding converts theses residues to efficient codewords. The lossless compression ratio (CR) of the proposed EC is as high as 2.24 on average, saving memory bandwidth by 55.4%. This EC algorithm is implemented using CMOS 0.18[Formula: see text][Formula: see text]m technology. The maximum throughput can reach 6.4[Formula: see text]Gpixels/s, which can accommodate 3840 × 2160@60fps. The experiment results demonstrate that this study presents better hardware efficiency of 337[Formula: see text]Gpixels/J and 83.5[Formula: see text]Kpixels/s/gate.

SPIHT Algorithm With Adaptive Selection of Compression Ratio Depending on DWT Coefficients

In mobile multimedia devices, the frame memory compression (FMC) technique by embedded compression (EC) is becoming an increasingly important video-processing method for reducing the external data bandwidth requirement, which, in turn, results in power savings. Among various EC schemes, the combination of discrete wavelet transform (DWT) and set partitioning in hierarchical trees (SPIHT) is widely used for FMC because it achieves high compression efficiency with low computational complexity. However, there is room for improvement in the conventional DWT and SPIHT algorithm because it compresses all blocks with the same compression ratio without taking into account the correlation between DWT coefficients and the SPIHT algorithm. This study proposes a novel one-dimensional (1-D) DWT and SPIHT algorithm, which enhances the quality of the compressed video by internally applying an adaptive compression ratio for the SPIHT algorithm based on DWT coefficients while keeping the same bit-stream size. The block complexity is predicted from the distribution of DWT coefficients. Then, simple blocks are aggressively compressed with a low compression ratio, while the complex blocks are compressed with a high ratio. Furthermore, to achieve the best video quality, each compression ratio is decided by an optimization technique based on mathematical formulation. Precisely, the logarithm of mean squared error by the SPIHT algorithm is assumed to be linearly correlated with the logarithm of processed DWT coefficients. Experimental results are provided that support the aforementioned model. Compared to the conventional 1-D DWT and SPIHT algorithm, the proposed scheme remarkably improves the video quality by an average of 2.23 dB in peak signal-to-noise ratio when the target compression ratio for the SPIHT algorithm is 5/16.

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System

A low complexity block-based adaptive lossless image compression

For low power and lossless image compression, in this paper, a low complexity, block-based decomposition of subbands technology is proposed for embedded compression (EC) algorithm, which is ready for being implemented on a single-chip of FPGA. The proposed algorithm is based on high-speed pipeline architecture of 2-D lossless integer wavelet transformation (IWT) with 2-D Lossless Hadamard Transformation (LHT). In the proposed algorithm, the coefficients of a 2-D IWT are decomposed by 4×4 blocks to further remove redundancy, compared with direct encoder by EBCOT of JPEG2000. Considering the feature of the 2-D IWT, a different strategy is designed for LL-subband and non-LL subbands, which denotes DC prediction (DCP) and adaptive transformation method (ATM), respectively. DCP is used to remove the correlation between two adjacent blocks of LL-subband, and ATM is used to transform non-LL subbands by 2-D LHT selectivity. After further transformation, the coefficients are decomposed as truncated integer part (TIP) and truncated residue parts (TRP), considering the complexity of hardware implementation, TIP is encoded by Zero Running Length (ZRL) and Exp-Golomb (EG). TRP is encoded by a fixed length (FL) encoder after removed redundancy by the feature of 2-D LHT, when seen as bit patterns [1]. Experimental results show that the proposed EC algorithm can achieve a good compression performance as JPEG2000, and the coding latency can be decreased at an average of 43.9%. Another innovation of this paper is EC's hardware-friendly feature and easy hardware implementation, which are presented by a simple addition or subtraction of the LIWT and LHT, and need a small on-chip memory.

움직임 보상된 웨이블릿 기반의 비디오 코딩 시스템에 적용 가능한 임베디드 압축 코덱 알고리즘

In this paper, a low-complexity embedded compression (EC) Codec algorithm for the wavelet video coder is applied to reduce excessive external memory requirements. The EC algorithm is used to achieve a fixed compression ratio of 50 % under the near-lossless-compression constraint. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform stages compared with direct implementation of the wavelet video encoder of this paper. Furthermore, the EC scheme based on a forward adaptive quantization and fixed length coding can save bandwidth and size of buffer between DWT and SPIHT to 50 %. Simulation results show that our EC algorithm present only PSNR degradation of 0.179 and 0.162 dB in average when the target bit-rate of the video coder are 1 and 0.5 bpp, respectively.

웨이블릿 변환의 메모리 크기와 대역폭 감소를 위한 Prediction 기반의 Embedded Compression 알고리즘

본 논문에서는 JPEG2000 부호화 시스템의 과도한 메모리 요구 사항을 감소시키기 위해 예측 부호화 기반의 새로운 임베디드 압축(Embedded Compression, EC) 알고리즘을 제안한다. 본 논문의 EC 기법은 EC가 적용되지 않은 DWT 프로세서와 비교하여 DWT 과정에서 발생하는 임시적인 저주파 웨이블릿 계수들의 메모리 접근 및 크기를 50 %로 줄일 수 있다. 무손실의 영상 압축 시스템에 널리 쓰이면서 단순하지만 좋은 성능을 갖는 LOCO-I(LOw COmplexity LOssless COmpression for Image)와 MAP(Median Adaptive Predictor) 예측기를 제안한 EC 알고리즘에 적용하였다. 제안한 예측 기반의 EC 알고리즘은 예측 오차 값들을 인코딩하기 위하여 포워드 적응형 양자화와 고정 길이 코드를 사용한다. 시뮬레이션 결과를 통해 예측기가 LOCO-I와 MAP인 경우, 본 논문에서 제안한 EC 알고리즘에 의한 평균적인 PSNR 저하는 각각 0.48 dB와 0.26 dB임을 알 수 있다. 선행 논문 [9]에서 제안한 하다마드 변환(MHT) 기반의 EC 알고리즘과 비교하여 평균적인 PSNR이 약 1.39 dB 향상된다. In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].

JPEG2000의 웨이블릿 변환용 메모리 크기 및 대역폭 감소를 위한 새로운 Embedded Compression 알고리즘

JPEG2000 시스템에서 요구하는 메모리의 크기와 대역폭을 감소시키기 위하여 본 논문은 약간의 화질 손실이 있는 새로운 임베디드 압축(Embedded Compression) 알고리즘을 제안한다. 또한, 메모리 내의 압축된 데이터에 임의 접근성(Random Accessibility)과 짧은 지연 시간(Latency)을 보장하기 위해서 매우 단순하면서도 효율적인 하다마드(Hadamard) 변환 기반의 부호화 방식을 제안한다. JPEG2000 표준안의 알고리즘에 변경을 주지 않고, 제안한 EC 알고리즘을 통해 LL 임시 메모리의 크기와 코드블록 메모리의 크기를 약 2 배로 줄이며, 약 52~73%의 메모리 대역폭을 감소시킬 수 있다. To alleviate the size and bandwidth requirement in JPEG2000 system, a new Embedded Compression(EC) algorithm with minor image quality drop is proposed. For both random accessibility and low latency, very simple and efficient hadamard transform based compression algorithm is devised. We reduced LL intermediate memory and code-block memory to about half size and achieved significant memory bandwidth reductions(about 52~73%) through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

An embedded compression algorithm integrated with Motion JPEG2000 system for reduction of off-chip video memory bandwidth

In Motion JPEG2000, huge bandwidth requirement of off-chip memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a low complexity and lossless embedded compression algorithm is devised. And for both random accessibility and low latency, we propose simple and efficient entropy coding algorithm. We achieved significant memory bandwidth reductions (75%), without requiring any modification or performance degradation in JPEG2000 standard algorithm.

Low complexity embedded compression algorithm for reduction of memory size and bandwidth requirements in the JPEG2000 encoder

In this paper, a new and low-complexity embedded compression (EC) algorithm for the JPEG2000 encoder system is proposed to efficiently reduce memory requirements. The proposed EC algorithm is used to achieve a fixed compression ratio of 50% under the near-lossless compression constraint. Through the EC technique, the memory requirement for intermediate low-frequency coefficients during multiple DWT stages can be reduced by a factor of 2 compared with direct implementation of the JPEG2000 encoder. By jointly considering the coding flow of both block-based 2D-DWT and bit-plane coders, the EC scheme combines an efficient quantization and simple entropy coder to reduce memory transaction bandwidth between DWT and bit-plane coder (BPC) to 50%. Furthermore, this EC reduces the size of code-block memory from DWT to BPC. Experiment results based on standard test image benchmarks show that our proposed EC algorithm presents only PSNR degradation of 1.05 dB on average when the target compression ratio is fixed at 50%. Our EC can be applicable to the JPEG2000 encoding system to save memory size and bandwidth requirements with minor picture quality degradation. The proposed EC algorithm is also computationally simple, reducing latency time and creating sufficient accessibility.

Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine

In this paper, a low-cost compatible motion compensator is implemented and integrated into a macroblock-level three-stage-pipelined HDTV decoder, in which an embedded compression (EC) engine is realized as well. The decoder with EC engine is designed to reduce the power consumption and memory bandwidth requirement since memory accesses are reduced. In the motion compensator, a boundary judgment scheme for reference pixel fetching is proposed to provide seamless integration in HDTV video decoder for the block-based EC engines. Furthermore, a buffer sharing mechanism is adopted to reduce extra memory requirement involved by EC. The reference pixel fetching unit costs only 17.3 K logic gates when the working frequency is set to 166.7 MHz. On average, when decoding HD1080 video sequence, 30% memory access reduction and 24% memory power consumption saving are achieved when a near lossless EC algorithm is integrated in the video decoder. In other words, the proposed motion compensator makes the EC engine an integral part of a memory reduced decoder without extra cost. Additionally, since the work in this paper is based on EC schemes, the EC design criterion are discussed, and several useful rules on the selection of EC algorithm are addressed for the video decoder of corresponding VLSI architecture.

A 6.4 Gbit/s Embedded Compression Codec for Memory-Efficient Applications on Advanced-HD Specification

The embedded compression (EC) technique is applied to reduce the memory bandwidth and capacity in a display system. In this paper, the high-speed EC algorithm is proposed for advanced-HD specification. It mainly comprises three features: 1) the associated geometric-based probability model is developed to construct context-modeling mechanism without context-table; 2) develop content-adaptive Golomb-Rice code and geometric-based binary code as the entropy coding with minor order of context; and 3) provide the rate control mechanism to guarantee the saving ratio of memory bandwidth and capacity. With competitive coding efficiency, the computation-efficiency of the proposed EC algorithm is about 44% and 40% of FELICS and JPEG-LS. The proposed very-large-scale integration architecture of entire codec is implemented in TSMC 0.18- 1P6M CMOS technology. Based on pixel-based parallelism and segment-based parallelism techniques, the encoding/decoding capability reaches Quad Full-high definition (QFHD) (3840 × 2160) at 30 Hz. The maximum throughput is as high as 6.4 Gbit/s. Furthermore, with multi-level parallelism, the performance can be extended to QHD (2560 × 1440) at 120 Hz and QFHD at 120 Hz for the double frame rate technique.

A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding

Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thus far. In this paper, a lossless EC algorithm for HD video sequences and related hardware architecture is proposed. The proposed algorithm consists of two steps. The first is a hierarchical prediction method based on pixel averaging and copying. The second step involves significant bit truncation (SBT) which encodes prediction errors in a group with the same number of bits so that the multiple prediction errors are decoded in a clock cycle. The theoretical lower bound of the compression ratio of the SBT coding was also derived. Experimental results have shown a 60% reduction of memory bandwidth on average. Hardware implementation results have shown that a throughput of 14.2 pixels/cycle can be achieved with 36 K gates, which is sufficient to handle HD-size video sequences in real time.

Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System

In a typical portable multimedia system, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 62%, 66%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With TSMC 0.18 mum 1P6M CMOS logic process, the proposed EC codec engine can encode or decode CIF 30 frame per second video data and achieve power saving of more than 109 mW. The EC codec engine itself consumes only 2 mW power.