A low complexity block-based adaptive lossless image compression

Abstract

For low power and lossless image compression, in this paper, a low complexity, block-based decomposition of subbands technology is proposed for embedded compression (EC) algorithm, which is ready for being implemented on a single-chip of FPGA. The proposed algorithm is based on high-speed pipeline architecture of 2-D lossless integer wavelet transformation (IWT) with 2-D Lossless Hadamard Transformation (LHT). In the proposed algorithm, the coefficients of a 2-D IWT are decomposed by 4×4 blocks to further remove redundancy, compared with direct encoder by EBCOT of JPEG2000. Considering the feature of the 2-D IWT, a different strategy is designed for LL-subband and non-LL subbands, which denotes DC prediction (DCP) and adaptive transformation method (ATM), respectively. DCP is used to remove the correlation between two adjacent blocks of LL-subband, and ATM is used to transform non-LL subbands by 2-D LHT selectivity. After further transformation, the coefficients are decomposed as truncated integer part (TIP) and truncated residue parts (TRP), considering the complexity of hardware implementation, TIP is encoded by Zero Running Length (ZRL) and Exp-Golomb (EG). TRP is encoded by a fixed length (FL) encoder after removed redundancy by the feature of 2-D LHT, when seen as bit patterns [1]. Experimental results show that the proposed EC algorithm can achieve a good compression performance as JPEG2000, and the coding latency can be decreased at an average of 43.9%. Another innovation of this paper is EC's hardware-friendly feature and easy hardware implementation, which are presented by a simple addition or subtraction of the LIWT and LHT, and need a small on-chip memory.