Scalar Multiplication In Elliptic Curve Cryptography Research Articles

Efficient Cryptographic Hardware for Safety Message Verification in Internet of Connected Vehicles

An important security requirement in automotive networks is to authenticate, sign, and verify thousands of short messages per second by each vehicle. This requirement mandates the use of a high speed Elliptic Curve Cryptography (ECC) hardware. The Residue Number Systems (RNS) provide a natural parallelism and carry-free operations that could speed-up long integer arithmetics of cryptographic algorithms. In this article, we propose a high-speed RNS Montgomery modular reduction units with parallel computing to reduce the latency of the field modular operations. We propose a fully RNS-based ECC scalar multiplication co-processor for NIST-P256r1 and Brainpool256r1 standard curves and improved the scalar multiplication speed using NAF and DBC numbering systems. Compared to the literature, our scheme provides faster computation without compromising the security level. The performance of our fully RNS-ECC point multiplication meets the requirements of the automotive industry.

Evaluation Study of Elliptic Curve Cryptography Scalar Multiplication on Raspberry Pi4

The internet of things (IoT) is defined as a collection of autonomous devices that connect and network with each other via the Internet without the requirement for human interaction. It enhances daily our lives such as through personal devices, healthcare sensing, retail sensing, and industrial control, as well as the smart homes, smart cities, and smart supply chains. Although the IoT offers significant benefits, it has inherent issues, including security and privacy risks, memory size limitations, and processing capability challenges. This paper describes the application of elliptic curve cryptography (ECC) in a simulated IoT environment to ensure the confidentiality of data passed between the connected devices. Scalar multiplication represents the main operation of ECC, and it is primarily used for key generation, encryption, and decryption. The aim of this paper is to evaluate and show the efficiency of adapt lightweight ECC with an IoT devices. In the study outlined in this paper, scalar multiplication was implemented on Raspberry Pi4 and processing time and consumed energy were measured to compare the performance. The comparison was made on the scalar multiplication of both fast and basic ECC algorithms. The result of the performance test revealed that a fast scalar multiplication reduced the computation time in comparison with basic scalar multiplication while consuming a similar level of energy.

A Hybrid Addition Chaining Based Light Weight Security Mechanism for Enhancing Quality of Service in IoT

IoT in Wireless Sensor Networkis a network of physical objects connected to internet such as RFID and sensors. As these types of objects have limited computation power and memory, execution of public key cryptography would be a daunting task. So a light weight encryption with Elliptic Curve Cryptography (ECC) is proposed in this work. A major issue in ECC is its computational cost as it is complicated to compute the scalar multiplication. To address this issue, a novel method called graph based addition chaining (GBAC) is proposed. This graph technique produces all possible optimum addition chains for the given integer n by utilizing edge weight of all possible numbers created from each number of addition chain. This addition chain technique can be used in modular exponentiation which is an essential step in the implementation of public cryptographic algorithms like ElGamal, RSA, etc., so that the time for encryption and decryption for these algorithms can be reduced drastically. The proposed GBAC technique has used addition chaining technique instead of scalar multiplication in ECC which greatly reduces the computation time as well as computation cost. It also reduces the complexity in ECC. Numerous experiments has been made and proved that our work decreases the decryption time by at least 10% than RSA algorithm, reduces computation cost and improves the performance of parameters like CPU time, Memory requirement and key preparation time and better than RSA in decryption.

A Novel Efficient Hardware Implementation of Elliptic Curve Cryptography Scalar Multiplication Using Vedic Multiplier

A Novel Efficient Hardware Implementation of Elliptic Curve Cryptography Scalar Multiplication Using Vedic Multiplier

Differential Fault Attacks and Countermeasures in Elliptic Curve Cryptography

In asymetric cryptography, Elliptic Curve Cryptography (ECC) is the fastest in term of computation and the strongest in term of security. It can be used in message encryption/decryption, digital signature or key exchange. ECC can be implemented in hard over binary field GF(2 n ) or in soft over prime field GF(p). This paper presents an efficient software implementation of ECC scalar multiplication over prime field using GNU Multiple Precision (GMP) Library. The differential fault attacks (DFA) on the RSA cryptosystem can be extended to ECC one by inserting bit errors during computation. In this paper, a ”No Correctness Check for Input Points” (NCCIP) attacks was applied and a countermeasures was given to protect ECC cryptosystem against it. Software implementation in C language, using GMP library, was simulated on Intel(R) Core(TM) i3 CPU M380 @ 2.87GHz(3 GB RAM, 32-bit architecture).

A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(<i>p</i>)

Field Programmable Gate Array (FPGA) implementation of Elliptic Curve Cryptography (ECC) over GF(p) is commonly not fast enough to meet the request of high-performance applications. There are three critical factors to determine the performance of ECC processor over GF(p): multiplication structure, modular multiplication algorithm, and scalar point multiplication scheduling. This work proposes a novel multiplication structure which is a two-stage pipeline on the basis of Karatsuba-Ofman algorithm. With the proposed multiplication structure, we design a 256-bit modular multiplier based on Improved Barret Modular Multiplication algorithm. Upon the modular multiplier, we finish the scalar point multiplication scheduling and implement a high-performance ECC processor on FPGA. Compared with the previous modular multipliers, our modular multiplier reduces the 256-bit modular multiplication time by 28% at least. Synthesis result on Altera Stratix II shows that our ECC processor can complete a 256-bit ECC scalar point multiplication in 0.51ms, which is at least 1.3 times faster than the currently reported FPGA ECC processors over GF(p).

Shifting primes: Optimizing elliptic curve cryptography for 16-bit devices without hardware multiplier

Security for the Internet of Things (IoT) presents the challenge of offering suitable security primitives to enable IP-based security protocols such as IPSec and DTLS. This challenge is here because host-based implementations and solutions are not providing a proper performance over the devices used in the IoT. This is mainly because of the use of highly constraint devices in terms of computational capabilities. Therefore, it is necessary to implement new optimized and scalable cryptographic primitives which can use existing protocols to provide security, authentication, privacy and integrity to the communications. Our research focus on the mathematical optimization of cryptographic primitives for Public Key Cryptography (PKC) based on Elliptic Curve Cryptography (ECC). PKC has been considered, since the IoT requires high scalability, multi-domain interoperability, self-commissioning, and self-identification.Specifically, this contribution presents a set of optimizations for ECC over constrained devices, and a brief tutorial of its implementation in the microprocessor Texas Instrument MSP430 (Briel, 2000) [1] (commonly used in IoT devices such as 6LoWPAN, active RFID and DASH7). Our main contribution is the proof that these special pseudo-Mersenne primes, which we have denominated ‘shifting primes’ can be used for ECC primitives with 160-bit keys in a highly optimal way. This paper presents an ECC scalar multiplication with 160-bit keys within 5.4 million clock cycles over MSP430 devices without hardware multiplier. Shifting primes provide a set of features, which make them more compliant with the set of instructions available with tiny CPUs such as the MSP430 and other 8 and 16-bit CPUs.

Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF( p )

This paper presents a reconfigurable hardware architecture for public-key cryptosystems. By changing the connections of coarse grain carry-save adders (CSAs), the datapath provides high performance modular operations that can be used for both RSA and elliptic curve cryptography (ECC). In addition, we introduce reconfigurable flip-flops in order to make an optimal choice of hardware resources. The proposed datapath is implemented with a 0.25-µm complementary metal oxide semiconductor (CMOS) technology and on a field programmable gate array (FPGA). We compare the performance of modular exponentiation for RSA and scalar multiplication for ECC based on the prototype implementation. The results show that higher performance is obtained for ECC on the same hardware platform.