Electrostatic Discharge Structures Research Articles

Research on ESD failure voltage model of the T-shaped wiring structure in GOA products

In the GOA (Gate on Array) circuits, which are commonly employed in LCD (Liquid Crystal Display) products, the metal wire layers have been found to be sensitive to ESD (Electrostatic Discharge) in production, leading to an increase in the failure rate of GOA products, especially in T-shaped wiring structures. In this paper, we conducted a study on the relationship between the ESD failure voltage and structure parameters of T-shaped wiring structures in GOA products to enhance their reliability. We established an ESD failure voltage model for T-shaped wiring structures based on the relevant electrical breakdown theory. And failure voltage and gap breakdown voltage data are required for accurate model parameters fitting. Hence, ESD tests on the T-shaped wiring structure samples were conducted. In addition, ESD simulation of T-shaped wiring structure using CST software was applied to supply gap voltage data unavailable from tests. Based on the results of the tests and simulation, parameters of the ESD failure voltage model were fitted. And we performed the model modification using verification tests for higher accuracy. The results show that our model errors are below 5 %. Guided by the ESD failure voltage model, a more reliable T-shaped structure can be produced in GOA.

Novel ESD device design for STT-MRAM memory chip

An investigation of the influence of the magnetic field induced by electrostatic discharge (ESD) current on magnetic tunnel junction (MTJ) device is presented in the paper. The transient magnetic field generated by the ESD current is not considered in the traditional CMOS ESD protection strategy, which may be a reason of the degradation of the performance and the robustness of STT-MRAM. An ESD protection circuit of STT-MRAM is proposed in the paper, including the diode-based ESD devices, the filter circuit and the power clamp. Based on the waveform analysis of the three ESD standard test models, including HBM, MM and CDM, a filter circuit is added in the ESD device to decrease the influence of the high frequency components on the magnetic device. The diode-based ESD devices are integrated in the ESD structure, which is used for the ESD window of STT-MRAM for its low operating voltage. Based on the operation mechanism of the STT-MRAM, its ESD window allows a low operating voltage, thus the diode-based devices are chosen to be integrated in the ESD device. The distribution and magnitude of the magnetic field are studied in the paper. The results show that the ESD protection circuit of STT-MRAM can effectively suppress the magnetic field generated by the ESD current, hence increasing the stability of STT-MRAM. Under the influence of the HBM, MM and CDM events, the ESD disturbance probability of the MTJ device are 2.0 × 10−12, 5.8 × 10−9 and 1.1 × 10−12 respectively. The influence of the memory density and the distance between pads and memory array are also investigated in this paper. The ESD protection strategy proposed in the paper can be adopted for the future high performance STT-MRAM.

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (<i>V</i><sub>H</sub>) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of <i>V</i><sub>H</sub> versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on <i>V</i><sub>H</sub> and holding current (<i>I</i><sub>H</sub>) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (<i>V</i><sub>DB</sub>) is affected by ambient temperature significantly, and the variation of <i>V</i><sub>DB</sub> dominates the variation trend of <i>V</i><sub>H</sub> with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of <i>V</i><sub>DB</sub>. The trend of <i>I</i><sub>H</sub> and parasitic Body resistance (<i>R</i><sub>Body</sub>) weakens the temperature dependence of the <i>V</i><sub>H</sub>. The current gain of parasitic bipolar transistor (<i>β</i>) decreases with ambient temperature rising, which is the main contributor to the decreasing of <i>I</i><sub>H</sub>. Therefore, increasing <i>I</i><sub>H</sub> and <i>R</i><sub>Body</sub> is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.

Analyze Scalable Sudoku-Type DTSCR ESD Protection Array Structures in 22nm FDSOI

This paper reports the design and analysis of scalable Sudoku-type diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharge (ESD) protection structures fabricated in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI) technology. 3D TCAD and ESD testing confirm that the Sudoku DTSCR ESD structures can dramatically improve the ESD area efficiency. Transmission line pulse (TLP) measurement shows a high ESD area efficiency of 6.47mA/mum2 for Sudoku-DTSCR, 64.6% improvement over traditional finger-DTSCR structure. A scalability model was derived as design guidelines for optimizing Sudoku DTSCR ESD protection array structures.

Mm‐wave power control

mm‐wave power control

Deep Trench Capacitor in Three Dimensional Through Silicon via Keepout Area for Electrostatic Discharge Protection

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip size. This requires growing products in the z-direction by building stacked chips (3-D chips). To optimize 3-D product costs, the area consumed by other processing requirements such as electrostatic discharge (ESD) protection needs to be as efficient as possible. Placing ESD structures made with deep trench capacitors in 3-D through silicon via keepout areas optimizes silicon area since these structures enable placement of ESD devices in space that would otherwise not be used.

Novel Nanophase-Switching ESD Protection

This letter reports the proof-of-concept results for the new nontraditional nanophase-switching electrostatic-discharge (ESD) protection mechanism and nanocrossbar ESD structures. Experiment shows good ESD switching and protection, i.e., a fast response of 100 ps, a ultralow leakage of 0.26 pA, and an ESD protection of >; 267 V/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A new dispersed local ESD tunneling model is proposed, and heterogeneous complementary metal-oxide-semiconductor integration is developed.

Analysis and Measurement of Signal Distortion due to ESD Protection Circuits

Electrostatic discharge (ESD) protection circuits typically contain a significant amount of nonlinear capacitance. At high frequencies and large amplitudes, this nonlinearity can degrade the signal integrity at the input pins of high performance mixed signal ICs, such as analog-to-digital converters (ADCs). This study provides a theoretical analysis of this problem as well as experimental results that quantify typical distortion levels introduced by state-of-the-art ESD structures. It is shown that with distortion targets nearing -100 dBc at signal frequencies on the order of 100MHz, ESD circuits will become a limiting factor in the future. In addition to these results, this study offers some brief guidelines for designing ESD protection circuits suitable for high-speed, high-linearity applications

On-chip electrostatic discharge protection for CMOS gas sensor systems-on-a-chip (SoC)

An on-chip electrostatic discharge (ESD) protection scheme is demonstrated for an emerging technology of microelectromechanical systems (MEMS)-based embedded sensor (ES) system-on-a-chip (SoC). The ESD protection scheme is implemented using ground-referenced multifinger thyristor-type devices optimized for (1) the input/output (I/O) protection, (2) the power supply clamp, and (3) the internal sensors’ electrodes during the micromachining process. The ESD structure developed demonstrates a leakage current below 10 −10 A, high on-state conductance, and high level of human body model (HBM) immunity.

A new ESD protection structure for high-speed GaAs RF ICs

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 /spl Omega/ at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD.

Optimization of on-chip ESD protection structures for minimal parasitic capacitance

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-μm CMOS technology has been presented and verified.

A study of parasitic effects of ESD protection on RF ICs

This paper presents a comprehensive study on influences of on-chip electro-static discharge (ESD) protection structures on performance of the circuits being protected. Two novel compact low-parasitic ESD structures were designed for RF and mixed-signal (MS) integrated circuits. Parasitic models of the ESD structures are extracted. RF building-block circuits, including a low-power high-speed op amp and a fully integrated 2.4-GHz low-noise amplifier were designed in 0.18/0.35-/spl mu/m technologies. Investigation of performance of these circuits under influences of the two new ESD protection structures and traditional MOS ESD protection device, in both copper and aluminum interconnects, demonstrated that significant circuit performance degradation (/spl sim/30%) occur when using NMOS ESD protection in Al technology, which recovered substantially (/spl sim/80%) when using low-parasitic ESD protection in Cu technology. This work indicates that the ESD-to-circuit influence is inevitable and substantial. Therefore, novel low-parasitic ESD protection solution is essential to maintaining both circuit functionality and ESD robustness in RF and MS applications.

A new pad-oriented multiple-mode ESD protection structure and layout optimization

This work reports a new multiple-mode pad-oriented electrostatic discharge (ESD) protection structure, which protects input-output pads against ESD pulses of all modes. A unique pad-based quasi-symmetric layout design is devised to improve ESD robustness. The new ESD structure features tunable triggering voltage, low holding voltage, low on-impedance, low leakage (/spl sim/pA), fast response time (/spl sim/0.18 ns), and low parasitic effect. It can be placed under a bond pad and consumes little silicon. It passed 14 kV human body model and 15 kV air-gap International Electrotechnical Commission ESD zapping. It was demonstrated in commercial BiCMOS processes and is suitable for multiple-supply mixed-signal, parasitic-sensitive RF and high-pin-count ICs.

On a dual-polarity on-chip electrostatic discharge protection structure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of /spl sim/0.18 ns, low leakage (/spl sim/pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of /spl sim/80 V//spl mu/m width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly.

A novel on-chip electrostatic discharge protection design for RF ICs

A novel, compact electrostatic discharge (ESD) protection structure is designed, which protects integrated circuits (ICs) against ESD damages in all modes. This ultra-fast-response ESD structure, with response time of t1∼0.16nS, operates symmetrically. Measurements showed desired low holding voltage (∼2V), low discharging impedance (<2Ω), high current handling capacity and adjustable triggering voltages. ESD testing passed HBM 14 and 15kV air-gap IEC zapping. Design prediction was achieved by comprehensive mixed-mode ESD simulation. The area-efficient ESD design features small Si consumption, low parasitic effects and is particularly suitable for high-speed VLSI and RF ICs. The design was implemented in commercial sub micron BiCMOS technologies for multi-power-supplies mixed-signal ICs.

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

The effect of scaling on electrostatic discharge (ESD) robustness in 1.2 to 0.25 μm channel length CMOS technologies is explored for ESD protection circuits and MOSFET structures. Results show that ESD robustness decreases as ESD structures are scaled to smaller dimensions in future technologies. Technology benchmarking, using a standardized ESD design, for evaluating ESD robustness is discussed. The ESD sensitivity of ESD designs to geometrical and semiconductor process parameters are evaluated. An analytical development for electro-thermal failure is developed based on electro quasi-static and adiabatic assumptions. ESD scaling relationships are developed applying MOSFET constant electric field scaling theory. ESD robustness scales as 1/α 3 2 , where α is the scaling parameter. The scaling relationship derived from the analytical model is then compared to established power-to-failure ESD models. The impact of MOSFET scaling on the ESD robustness of MOSFET structures is then discussed. MOSFET scaling as a function of technology generation shows that snapback breakover and sustaining voltages are decreasing with each technology generation. Optimization, design constraints and technology tradeoffs in CMOS technology development are then shown using a design curve methodology.