Electrostatic Discharge Robustness Research Articles

Investigation on MOS shunt LVTSCR for ESD application

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/μm without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

ESD Research of SCR Devices under Harsh Environments.

In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System

The papers in this special issue focus on scientific contributions in the field of electrostatic discharge (ESD) and immunity—from integrated circuits (ICs) to system. ESD can damage or disrupt electronic systems. With continued scaling of ICs, a combined approach of IC and system forms the best path for understanding and ensuring robustness. This relates to the IC itself: input/output (I/O) structures, power distribution network (PDN), interfaces between IP blocks, as well as the interaction of external protection devices with internal ESD protection structures during system level stress. To effectively protect the ICs fabricated in the advanced nanoscale CMOS processes, the turn-on speed of ESD protection devices must be enhanced to quickly discharge ESD current before the internal circuits are damaged by ESD stresses. Not only component level ESD events, the system level ESD test specified in the IEC 61000-4-2 standard has been used to verify ESD immunity of the microelectronics products. During system level ESD testing, the ESD problems relates to soft failures. So far, only few models for soft failures have been reported. It becomes visible that well designed hard failure protection can also reduce the likelihood of soft failures as most of the current is diverted from the IC and will not disturb the PDN of the IC. ESD robustness in the system level and component level are both important to meet the electromagnetic compatibility (EMC) regulations and/or standards in the industry.

Degradation Behavior and Mechanism of SiC Power MOSFETs Under Repetitive Transmission Line Pulse Stress

The electrostatic discharge robustness of silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated by the transmission line pulse (TLP) method. The degradation behavior of key electrical parameters of the device under repetitive TLP stress is investigated. A decrease in threshold voltage, an increase in gate leakage current, and the degradation of gate capacitance parameters are observed compared with the prestress values. Low-frequency noise (LFN) test results show that after multiple TLP stress cycles, the typical leakage current noise of the device increases by approximately one order of magnitude compared to prestress, which means that the trap density extracted based on the McWhorter model increases by one order of magnitude after 1000 TLP stress pulses. Furthermore, sources of defects in the gate oxide dielectric of the devices after stresses are analyzed. The physical mechanism of the changes of SiC MOSFETs characteristics could be attributed to the hole trapping by oxygen vacancy defects and single carbon interstitial in the oxide layer after TLP stresses, which induces an electrostatic effect and results in the changes in the electrical properties of the devices. The results may be useful in the design and application of SiC power MOSFETs.

Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

The I/O of CMOS integrated circuits of for FlexRay communication has to be tolerant with the input signals of ±60 V in its normal applications. Thus, the on-chip electrostatic discharge (ESD) protection devices for such I/O pin must be kept off unless the bus voltage is higher than 60 V or lower than −60 V. In this work, the bi-directional p-n-p (Bi-PNP) device was proposed and optimized for bi-directional ESD protection in the FlexRay communication systems. The proposed Bi-PNP devices were verified in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology. The relationships between the layout spacing of doping layers and other device characteristics, including trigger voltage (Vt1) and breakdown voltage (BV), were investigated, respectively. The size dependence on the ESD robustness was also studied. The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated. Finally, the recommended size and parameters of the proposed Bi-PNP device for ±60 V FlexRay application are provided.

Design of capacitor-less LDO regulator with SCR-based ESD protection using dual push-pull stage

ABSTRACT The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs

Gallium nitride (GaN) technologies have become an essential role in commercial advanced RF systems, which accompany emerging RF electrostatic discharge (ESD) reliability challenges. As opposed to ESD clamp transistors in <i>LV</i> CMOS technologies, a mis-correlation between standard-defined human body model (HBM) ESD robustness and commonly used TLP failure current was observed in GaN (MIS) high electron mobility transistors (HEMTs). Using transient HBM <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics, a novel discharge model is proposed to explain the transient discharge mechanism. The TCAD and SPICE simulations confirmed that the observed mis-correlation between TLP and HBM is attributed to 2-dimensional electron gas (2DEG) resistance modulation in response to HBM ESD transient voltage waveforms. The HBM waveforms under full transient duration in terms of rising and falling edges are further discussed. Eventually, the failure mechanisms in the TLP IVs and the HBM transient IVs can be well correlated in GaN (MIS)HEMTs.

Analysis of HBM Failure in 3D NAND Flash Memory

Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

HV-LDMOS Device Engineering Insights for Moving Current Filament to Enhance ESD Robustness

In this article, a novel design approach for improving electrostatic discharge (ESD) robustness of high-voltage laterally double-diffused MOS (LDMOS) devices is presented using detailed 3-D TCAD simulations. The proposed method considers engineering both static filament and dynamic/moving current filaments in LDMOS design. Physical insights and engineering approaches for moving filaments at higher stress current levels are presented. Dynamic filament motion and its relation to n-p-n turn-on engineering with an optimum p-well profile and substrate biasing are revealed. A unique window failure in LDMOS near snapback is discussed for the first time. A detailed analysis is presented on filament width engineering by using optimum drain diffusion length (DL) and its influence on static filament-induced window failures. This approach resulted in ten-time improvement in ESD robustness for self-protecting concepts. Finally, different fundamental questions related to the origin of filament motion are explored (using 3-D TCAD) with the help of engineered LDMOS Designs.

A Novel AlGaN/GaN Transient Voltage Suppression Diode with Bidirectional Clamp Capability.

This work proposes a novel AlGaN/GaN transient voltage suppression (TVS) diode (B-TVS-D) with bidirectional clamp capability, which consists of a small-size AlGaN/GaN monolithic bidirectional switch, two 2DEG-based current-limiting resistors (R1A/R1C, in parallel connection between the gate electrodes and the neighboring ohmic-contact electrodes (anode/cathode)), and a 2DEG-based proportional amplification resistor (R2, in parallel connection between two gate electrodes). It is demonstrated that the proposed B-TVS-D possesses a symmetrical triggering voltage (Vtrig) and a high secondary breakdown current (Is, over 8 A, corresponding to 12 kV human body model failure voltage) in different directional electrostatic discharge (ESD) events. The proposed diode can effectively enhance the electrostatic discharge robustness for the GaN-based power system. It is also verified that R1A/R1C and R2 have an important impact on Vtrig of the proposed B-TVS-D. Both the decrease in R2 and increase in R1A/R1C can lead to the decrease of Vtrig. In addition, the proposed B-TVS-D can be fabricated on the conventional p-GaN HEMT platform, making the ESD design of the GaN-based power system more convenient.

Intrinsic ESD robustness on new high voltage N/PMOS devices in 28 nm FDSOI UTBB CMOS technology through TLP/VFTLP characterizations

The robustness of intrinsic electrostatic discharge (ESD) is a major topic for the fabrication of advanced CMOS technology and in particular for high voltage (HV) N/PMOS transistors. In this study, it is reported the way to fabricate a HV MOS in standard 28 nm fully depleted (FD) silicon on insulator (SOI) with ultra-thin body and BOX (UTBB). This new device is without extra technology steps and without extra cost. This solution is based on layout design approaches with different flavours of back gate. Afterwards, DC characterizations on booth N & P MOS transistors are presented and discussed. The next step is to investigate the intrinsic ESD robustness on these devices through transmission line pulse (TLP) characterization at room temperature. It appears an interesting intrinsic robustness for this kind of devices. These preliminary results will be useful to use these devices in HV applications with a dedicated ESD protection and this solution lead to be more competitive on FDSOI technology nodes.

Large array device characteristics improvements

Large array devices are often used for big current driving capabilities in power electronic integrated circuit (IC) applications. Since these structures have big sizes, typical electrostatic discharge protection methodologies cannot be applied in such kind of IC. Otherwise, IC will become too huge to marketing. In this paper, a novel signal control switching architecture for adding large array devices' ESD performances is proposed. Only a little layout area is increased, but a huge electrostatic discharge robustness improvement can be obtained. Moreover, electrical safe operation area characteristics of large array devices are also improved very much with this new scheme. This study is processed in 0.15 μm Bipolar CMOS DMOS (BCD) with silicide technologies.

Simulation Study of a High Gate-to-Source ESD Robustness Power p-GaN HEMT With Self-Triggered Discharging Channel

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , and a proportional amplification resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness.

All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper proposes a design for a wholechip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 ㎛ bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests.

A compact broadband ESD protection circuit using multi‐layer helical inductor

Here, a broadband electrostatic discharge (ESD) protection circuit using area-efficient multi-layer helical inductors is presented. The proposed concept was verified in a 0.18 μm 1P6M CMOS process, and the circuit area is only 54 × 63 μm2. The measurement results show that a bandwidth of around 30 GHz is achieved, and the impedance matching is kept under –20 dB up to 40 GHz. The measured TLP and VF-TLP currents reach 2.19 and 5.80 A, respectively, which indicates a good ESD robustness.

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.