Electrostatic Discharge Pulse Research Articles

Electrostatic discharge induced degradation of optical-electrical properties and defect evolution of GaAs-based oxide-confined VCSELs.

GaAs-based oxide-confined vertical-cavity surface-emitting lasers (VCSELs) exhibit relatively low resistance against reliability-related damage. In order to gain a deeper understanding of the degradation and failure mechanism in oxide-confined VCSELs caused by electrostatic discharge (ESD)-induced defect proliferation, we investigated the effects of ESD stress on the degradation of optical-electrical characteristics and the evolution of defects in VCSELs under human body model test condition. The degradation threshold values for forward and reverse ESD pulse amplitudes were estimated to be 200 V and -50 V, respectively. Notably, VCSELs demonstrated greater sensitivity to reverse bias ESD compared to forward bias ESD. Analysis of optical emission and microstructure provided evidence that the device failure is attributed to an increase in ESD current density, leading to the multiplication of dark line defects (DLDs) originating from the edge of the device's oxide aperture. The formation of defects occurred suddenly in discrete events within small regions, rather than progressing gradually and uniformly. These defects propagated and led to damage across the entire active region. We believe that our results would be meaningful for improving the reliability of VCSEL in the future.

TLP/VFTLP investigation on eNVM 1T1R PCM in FD-SOI UTBB CMOS technology at room temperature

Intrinsic robustness against electrostatic discharge (ESD) like HBM or CDM is a major concern for the reliability and functionality in advanced CMOS FD-SOI technology and especially for non-volatile memory (eNVM). And it is well known that device characterizations are a first step of an ESD investigation. Thus, this R&D study the experimental results from 100 ns to 1 ns transmission line pulse (TLP-VFTLP) on 1T1R phase change memory (PCM) at 300 mm wafer level and at room temperature are reported here. Two types of devices are fabricated and characterized in the standard fully depleted (FD) silicon-on-insulator (SOI) with ultra-thin body and BOX (UTBB). These devices have no additional technological step and are embedded in the final memory cell topology with its selector NMOS transistor. The idea is to evaluate the behaviour of the 1T1R device under transmission line pulse stress with different stress durations. TLP/VFTLP I-V curves are reported and discussed along with post-DC responses to determine the magnitude of the phase change generated by the ESD pulse. These characterizations are important for automotive, micro-controllers, neuromorphic computing and spatial applications depending on their dedicated mission profiles at room or cryogenic temperature.

Removal of powders from cavities in contaminated surfaces by shock and plasma generated by an adjacent electro-static discharge

An electrostatic discharge (ESD) produced between pin electrodes above a cavity filled with powder is explored as means of contactless removal of particles from contaminated surfaces. The ESD is produced by discharging a capacitor through an air gap. Glass beads of different sizes serve as model powders filling cavities of different depths. Masses of both loaded and ejected powders are measured. The motion of the ejected particles is studied using high-speed video. Most of the ejected particles move vertically up with the initial velocities varied from ca. 4 to 11 m/s. Changing the mechanical properties of the substrate holding the powder does not significantly affect the velocities of the ejected particles. For powders removed from cavities as a result of interaction with the shock and plasma produced by ESD, the number of particle layers ejected is determined by the particle size and the ESD energy, but is not significantly affected by the cavity depth. A single ESD pulse can be effective in the complete removal of powder particles from relatively shallow, 0.2-mm deep cavity. Estimates suggest that the particles are primarily ejected due to the lift forces produced by local velocity gradients of the gas above the loaded powder layer.

ESD-Event Detector for ESD Control Applications in Semiconductor Manufacturing Factories

An electrostatic discharge (ESD)-event detector has been designed and fabricated in a single chip to detect and alarm the ESD events in semiconductor or integrated circuit (IC) manufacturing environments. The experiment measured results showed that the peak-to-peak voltage of the detected signal during an ESD event has a strong correlation with its ESD-stress voltage level. <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The proposed ESD-event detector can determine a</b> detected <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signal to be an ESD pulse if its signal amplitude is higher than the settable threshold and its duration time is under 500 ns.</b> The ESD-event detector circuit, including a <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">450 MHz</b> logarithmic amplifier, a comparator, and a time discriminator, has been implemented in a single chip with a total silicon area of only 693 × 563 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\mathbf{m}}^2$</tex-math></inline-formula> and fabricated by 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS process. <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The detector can detect high-frequency transient signals up to 450 MHz, which has been successfully verified in the field tests by detecting the signals generated from the ESD generators, the human-body model tester, and the field-induced charged-device model tester.</b> The proposed ESD-event detector can efficiently perform the real-time ESD monitoring applications in the IC and semiconductor manufacturing factories.

Investigation of Frequency Models to Predict Dynamic Behavior of ESD Protection Networks

With the shrinking dimension of technologies and safety requirements, electrostatic discharge (ESD) protections play a more and more important role. Consequently, the prediction of the transient behavior's protection network is becoming difficult for system level designers in order to guarantee systems safety. A model reproducing the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior is needed to obtain a precise simulation's protection strategy network, especially during the protection triggering. In this article, we propose a complete measurement and computation setup to access an equivalent frequency model of devices under strong pulse injections for a rapid model construction. Details of the measurement and data computation to obtain a frequency model using a transmission line pulse generator combined with time-domain reflectometry measurement will be provided. To validate our proposed frequency model, a comparison between the measurements and simulations is first performed on passive and linear components, and then on two protection devices (transient voltage suppressor). A simulation on a protection network, at the board level, will show that the combination of the frequency models could be done to predict its response to ESD pulse with an acceptable precision, without the tedious step of component modeling.

Research on Turn-On Characteristics of New Light-Triggered Silicon Controlled Rectifier for Dual-Directional Electrostatic Discharge Protection

Dual-direction silicon-controlled rectifiers (DDSCRs) have been generally applied for bidirectional electrostatic discharge (ESD) protection due to their excellent robustness. However, the traditional DDSCR has a longer discharge path, which makes its turn-on speed relatively slow. In view of this problem, this paper proposes a light-triggered SCR (LTSCR). The device uses the depletion region of the DN-Well/P-Well to absorb photons and generate photogenerated carriers to facilitate the formation of SCR loop. Under the action of light triggering, the LTSCR can form a low-resistance SCR loop faster and effectively discharge the ESD pulse. Using the forward equivalent circuit model, the current relationships within the LTSCR device are analyzed. Furthermore, the working mechanism of the LTSCR is clearly described by Silvaco 2D device simulation and verified in transmission line pulse (TLP) test. Experimental results show that the LTSCR takes 7 ns less time to turn on under light compared to the dark environment. This light trigger method does not require special masks or any process modification during the fabrication process, and has wide adaptability.

Transient Response of ESD Protection Devices for a High-Speed I/O Interface

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode, where the diode's turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> may prevent turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> , and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> . Adding a small passive impedance between the external TVS and the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode helps the TVS turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and reduce the current through the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode current by up to a factor of two.

Quasi-static analysis of susceptibility of the spacecraft power bus bar to the effects of electrostatic discharge

We performed a quasi-static analysis of susceptibility of the spacecraft power bus bar to the effects of electrostatic discharge (ESD). For the analysis, we used a schematic diagram of a power bus bar model with branch conductors. The schematic diagram consists of series-connected transmission lines, which represent the cross-sections of each power bus bar element. An ESD pulse with a current shape of fourth severity level was accepted as an excitation. The work shows the voltage waveforms at the beginning and end of the power bus bar when ESD impacts the branch conductors. We localized the maximum amplitude of the voltage in the bus section under ESD exposure. It revealed that when ESD affects the shielding tape covering the negative branch, there is a maximum attenuation (13.5 times) at the positive branch and a minimum attenuation (1.6 times) at the negative branch.

СПОСОБЫ ЗАЩИТЫ АППАРАТУРЫ СОТОВОЙ (МОБИЛЬНОЙ) СВЯЗИ ОТ ЭЛЕКТРОМАГНИТНЫХ ВОЗДЕЙСТВИЙ

Under electromagnetic impact (EMI) of a sufficient level, temporary disruption of functioning, processing, transmission and storage of information in cellular equipment is possible. Possible problems of electromagnetic compatibility (EMC) of a mobile phone and a base station (BS) of cellular connection under the influence of electromagnetic radiation (EMR) from other sources and their negative impact on functioning are considered. The energy of the HF electromagnetic field (EMF) after passing through the protective case can affect the devices of shielded radio electronic equipment (REE), therefore, the possible negative consequences of the impact of high-energy EMF on the REE are described. Possible negative consequences under certain conditions from the influence of the skin-effect, the effects of electrostatic discharge and electromagnetic pulses on electronic devices are given. It is shown that the constructional method of protecting REE from the effects of external electromagnetic factors consists in reducing the collected and transmitted EMF energy by improving the design, placement and installation of equipment. Components of some vendors for 5G systems that are resistant to external interference are given, and the possibilities for reducing the radiation level of a cell phone are noted. The necessity of an integrated approach to solving EMC problems is substantiated, which consists in the use of structural, circuitry and structural-functional methods of EMC provision. The new 5G (Fifth Generation) standard will operate at higher operating frequencies compared to previous generations. Due to the workload of the electromagnetic spectrum at frequencies below 6 GHz, 5G networks will be based on wireless radio access systems operating at frequencies of 30–100 GHz, that is, in the lower band of the extremely high frequency range EHF (Extremely High Frequency), 30–300 GHz.

СПОСОБЫ ЗАЩИТЫ АППАРАТУРЫ СОТОВОЙ (МОБИЛЬНОЙ) СВЯЗИ ОТ ЭЛЕКТРОМАГНИТНЫХ ВОЗДЕЙСТВИЙ

Under electromagnetic impact (EMI) of a sufficient level, temporary disruption of functioning, processing, transmission and storage of information in cellular equipment is possible. Possible problems of electromagnetic compatibility (EMC) of a mobile phone and a base station (BS) of cellular connection under the influence of electromagnetic radiation (EMR) from other sources and their negative impact on functioning are considered. The energy of the HF electromagnetic field (EMF) after passing through the protective case can affect the devices of shielded radio electronic equipment (REE), therefore, the possible negative consequences of the impact of high-energy EMF on the REE are described. Possible negative consequences under certain conditions from the influence of the skin-effect, the effects of electrostatic discharge and electromagnetic pulses on electronic devices are given. It is shown that the constructional method of protecting REE from the effects of external electromagnetic factors consists in reducing the collected and transmitted EMF energy by improving the design, placement and installation of equipment. Components of some vendors for 5G systems that are resistant to external interference are given, and the possibilities for reducing the radiation level of a cell phone are noted. The necessity of an integrated approach to solving EMC problems is substantiated, which consists in the use of structural, circuitry and structural-functional methods of EMC provision. The new 5G (Fifth Generation) standard will operate at higher operating frequencies compared to previous generations. Due to the workload of the electromagnetic spectrum at frequencies below 6 GHz, 5G networks will be based on wireless radio access systems operating at frequencies of 30–100 GHz, that is, in the lower band of the extremely high frequency range EHF (Extremely High Frequency), 30–300 GHz.

Ignition of zirconium powders placed near an electrostatic discharge

Abstract Electrostatic discharge (ESD) or spark produced by breakdown of a gap while discharging a capacitor is a common ignition stimulus for powders of reactive and energetic materials. It is a safety hazard, but is also used to initiate pyrotechnic formulations and as a characterization method of reactivity of energetic materials. In previous experimental studies, the powder served as one of the ESD electrodes. Ignition was found to be caused by Joule heating, with the main heat release by current passing through points of contact between particles. However, ignition may occur when the ESD does not pass directly through the powder. ESD generates a shock wave, which can lift the powder from a substrate even if the substrate is not an electrode. ESD also generates a plasma kernel heated to ca. 10,000 K, which exists for hundreds of µs, often much longer than the ESD current. Here, the effect of the ESD-induced shock and plasma on a reactive powder was studied experimentally for the first time. A thin layer of Zr powder was placed on a substrate located under a spark gap between two pin electrodes. Photo-sensors and high-speed video were used to document ignition and combustion events. The ESD energy and distance from the spark gap and powder were varied. At close distances, particles ignited consistently. Distance limits were determined, beyond which ignition was no longer observed. Higher ESD energies as well as longer ESD pulses led to ignition at greater distances. Ignition involved two distinct processes. First, submicron particles were lifted from the substrate on a time scale of single microseconds, interacted directly with the plasma kernel, and combusted. Optical emissions from this combustion lasted 100 – 600 µs, as expected for the burn time of submicron Zr particles in air. The second ignition event occurred several milliseconds later. It involved a flame propagating through Zr powder aerosol or combustion of individual lifted particles. This event was caused by coarser Zr particles radiatively heated during ESD. Importantly, the powder was aerosolized by convective flows caused by the rising plasma kernel making it possible for the self-heating of particles oxidizing in air to eventually lead to their ignition and combustion. Observed times for these delayed ignition and combustion events were in the order of tens of milliseconds.

Analysis and prediction of the stability of train control systems to ultra-wideband electromagnetic pulses of intentional action

Problem of ensuring stability of railway automation systems to ultra-wideband pulses of an electromagnetic field is considered. These pulses can be used to intentionally affect the equipment of these systems. It is shown that modern complex systems of control and safety of train traffic are vulnerable to electromagnetic impulses of intentional action. The features that determine the difference between the problem of ensuring the stability of railway automation systems from information systems are highlighted. In particular, microprocessor-based automation systems are geographically distributed and accessible for action from a short distance. The test generators used to prove immunity to electromagnetic impulses from intentional exposure are unique installations. Therefore, to reduce the number of tests design estimates and comprehensive tests for immunity to electromagnetic interference are required. Electrostatic discharges have the widest frequency spectrum. They act on the same apertures in the housings of technical means of railway automation systems as impulses of intentional action. The level of energy absorbed in electronic nodes can be calculated using the Rayleigh theorem. The electromagnetic field inside the housing is determined by the known relations for the radiation of the antennas and depends on the spectrum of the electric component of the field in the antenna aperture. This spectrum, in turn, depends on the spectrum of the electrostatic discharge pulse and the geometric parameters of the antenna. When an electromagnetic wave of an intentional impulse is incident, the aperture releases this impulse and transmits it into the housing. Therefore, the intentional impulse emitted into the housing and the electrostatic discharge impulse can be compared in shape and amplitude. Pulses of different shapes, in turn, can be compared using the spectral-energy equivalence condition. Intentional impulse equivalent to an electrostatic discharge impulse and, accordingly, having the same energy with it, causes exactly the same failures or setback of the element base. The amplitude of the pulse received by the aperture and the amplitude of the transmitted pulse are related by the utilization of the antenna. Thus, authors have obtained a technique for indirectly assessing the influence of an electromagnetic pulse of intentional action based on the calculated prediction of the resistance of railway automation systems to electrostatic discharges. An analogue of the equation of power suppression of radioelectronic means is obtained, which allows finding the parameters of an electromagnetic pulse generator that creates dangerous pulses for railway automation systems. Also, this equation allows calculating the size of the suppression zone for a given generator.

GaN 2DEG Varactor-Based Impulse Suppression Module for Protection Against Malicious Electromagnetic Interference

A GaN-based metal–semiconductor–metal varactor with a two-dimensional electron gas (2DEG) layer is proposed and fabricated. The capacitance variation of this fabricated varactor biased at different external voltages is studied and measured, and the frequency-dependent capacitance and resistance of the varactor are simulated by a corresponding empirical formula. A high-frequency protective filter is further constructed and placed under a large pulsed-current injection in a malicious electromagnetic interference immunity test. The results show that the proposed GaN-based module can reduce the large pulsed current to an acceptably small level. Thus, the GaN-based 2DEG varactor is an attractive candidate for applications designed to protect the upcoming 5G high-frequency system from risks such as electrostatic discharge, lightning, and electromagnetic pulses.

Reliability improvements in SOI‐like MOSFET with ESD and self‐heating effect

A new structure of N-type Silicon-on-insulator (SOI)-Like Bulk Silicon (N-SL-BS) metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to improve the reliability of SOI MOSFET mainly with regards to their self-heating effect and electro-static discharge (ESD) events based on two-dimensional numerical simulation. The new device employs p/n-/p + structure on Si, in which the n-layer is made of Si carbide (SiC), a wide bandgap material. The built-in electric field fully depletes the n-SiC layer and forms an SOI-like feature with a p + layer underneath. Simulations are first implemented in self-heating conditions, to investigate their drain current and temperature ramping. More importantly, ESD pulses assuming the human body model are applied to test their response and observe which device was first to fail using an I-V curve and hole current density distribution. Results show that the new device exhibits superior reliability when compared with a traditional SOI MOSFET. The avalanche breakdown voltage improves nearly 33% and the highest temperature of the global device is more than three times lower than that of an SOI MOSFET subjected to ESD pulses with a peak current of 7 mA.

Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events

The RC -based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18- $\mu \text{m}$ 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage ( ${V}_{\text {starting}}$ ) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 °C under normal power-ON condition.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{r})$ </tex-math></inline-formula> and duration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{d})$ </tex-math></inline-formula> was performed across a wide temperature range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T = -30/+110~^{\circ }\text{C}$ </tex-math></inline-formula> ). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> ), width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> ), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

System-Level Modeling for Transient Electrostatic Discharge Simulation

This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C , ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system's response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power–time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction's microscopic geometry, material information, defect location, or melting temperature.

SCR 기반 양방향성 ESD보호회로의 설계 변수 변화에 따른 전기적 특성의 관한 연구

본 논문에서는 높은 홀딩 전압을 갖는 SCR(silicon-controlled rectifier)기반 양 방향성 ESD 보호회로를 제안하였다. 일반적인 ESD 보호회로와 달리 양방향의 ESD Stress mode의 방전경로를 제공하며 높은 홀딩전압으로 latch-up면역 특성을 갖어 효과적인 ESD보호를 제공한다. 또한, 높은 홀딩전압을 위한 설계변수인 Gate Length와 N+bridge Length의 길이 변화에 따른 시뮬레이션을 Synopsys사의 TCAD 시뮬레이터를 사용하여 확인 하였다. 시뮬레이션 결과 2.1V에서 6.5V까지 홀딩 전압의 증가로 latch-up 면역 특성을 개선 하였으며, 기존 SCR보다 6.5V의 낮은 트리거 전압특성을 갖고 있어 제안된 ESD 보호 회로는 5V 이상의 공급전압을 갖는 application에 적용 가능하다. In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using Bipolar-CMOS-DMOS technology, with width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

High efficiency and enhanced ESD properties of UV LEDs by inserting p-GaN/p-AlGaN superlattice

Significantly improved electrostatic discharge (ESD) properties of InGaN/GaN-based UV light-emitting diode (LED) with inserting p-GaN/p-AlGaN superlattice (p-SLs) layers (instead of p-AlGaN single layer) between multiple quantum wells and Mg-doped GaN layer are reported. The pass yield of the LEDs increased from 73.53% to 93.81% under negative 2000 V ESD pulses. In addition, the light output power (LOP) and efficiency droop at high injection current were also improved. The mechanism of the enhanced ESD properties was then investigated. After excluding the effect of capacitance modulation, high-resolution X-ray diffraction (XRD) and atomic force microscope (AFM) measurements demonstrated that the dominant mechanism of the enhanced ESD properties is the material quality improved by p-SLs, which indicated less leakage paths, rather than the current spreading improved by p-SLs.