Electrostatic Discharge Protection Capability Research Articles

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

An ESD robust high holding voltage dual-direction SCR with symmetrical I-V curve by inserting a floating P+ in PWell

The dual directional silicon-controlled rectifier (DDSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its bi-directional ESD protection and strong current-tolerating capability per area. In this paper, an asymmetrical dual directional ESD protection device for automotive application was developed in a 0.18-µm Bipolar CMOS DMOS (BCD) technology. In order to verify and predict the proposed ESD protection device’s characteristics, a transmission line pulse (TLP) testing system and a 2-dimension device simulation platform have been used in this work. According to the measurement results, the asymmetrical dual directional silicon-controlled rectifier with a floating P+ region (ADDSCR_FP+) increases the forward holding voltage (Vh) from 3.89 V to 19.7 V and increases the reverse holding voltage from 3.62 V to 19.5 V which only slightly decrease the failure current compared with the traditional asymmetrical dual directional silicon-controlled rectifier (ADDSCR). The ADDSCR_FP+ has the features of symmetrical forward and reverse I-V curves, high holding voltage and high failure current.

Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.

Pin-pin ESD protection for electro-explosive device under severe human body ESD

Electrostatic discharge (ESD) may introduce huge damages to electro-explosive devices (EEDs). This paper studies the pin-pin ESD protection for EED under server human body ESD. We use the PSpice and MATLAB to simulate the ESD of EED protected with transient voltage suppressor (TVS), varistor, semiconductor arrester and capacitance. Moreover, we achieve the decay time, current waveforms, voltage waveforms and energy integration waveforms of the EED during the ESD, with different protections. Simulation results reveal that TVS succeeded in protecting bridgewire EED against the pin-pin ESD, while other three did not provide adequate protection. The pin-pin ESD experiments have been performed using the TVS and varistor. Experimental results show that, using the TVS protection, the EED is not firing under the severe 50kV ESD voltage. However, by using varistor protection, the ESD protection capability increases by more than 90%, while the protection capability only enhances by 3.1%. The response time of the TVS, i.e. 10−12s, is much faster than that of the varistor, i.e. 10−8s.

Impact of three-dimensional stacking silicon on diamond substrate for the electrostatic discharge protection device

In this paper, the electrostatic-discharge (ESD) protection capabilities of the protection devices fabricated on a silicon-on-diamond (SOD) structure and a conventional Si substrate are compared. The results showed that the ESD protection capability of the SOD substrate is higher than that of the silicon-on-insulator (SOI) substrate. We also evaluate the ESD protection device suitable for the SOD structure. In addition, we propose the three-dimensional (3D) stacking structure suitable for a power supply on a chip (power-SoC) and the best location for the implementation of the ESD protection device based on the results of device simulations.

An Area-Efficient Clamp Based on Transmission Gate Feedback Technology for Power Rail Electrostatic Discharge Protection

An area-efficient clamp based on transmission gate feedback technology is presented for power rail electrostatic discharge (ESD) protection. With this novel design, only a time constant of 10 ns is required for triggering and keeping the clamp turn-on during an ESD event. Full chip ESD protection with this design can endure a human body model pulse of 4500 V. Compared with the conventional clamp with the same area, the proposed clamp has 28% improvement in ESD protection capability. Simulation results show that there is no mistriggering problem caused by power-on pulse and power noise.

Electro-Static Discharge Protection Design for V-Band Low-Noise Amplifier Using Radio Frequency Junction Varactor

The RF junction varactors are employed as electro-static discharge (ESD) protection devices and co-designed with 60 GHz low-noise amplifier (LNA) fabricated in a 65-nm CMOS technology. The junction varactor acts as an ESD diode to bypass ESD current during ESD zapping, and also utilized as a capacitor to be a part of input matching network of the LNA in normal RF operation. By transmission line pulse (TLP) measurement, the ESD protection capabilities of RF junction varactors are characterized with different device parameters. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD levels to parasitic capacitances (VESD/CESD). With ESD/matching co-design methodology, the ESD-protected LNA demonstrates a second breakdown current It2 of 1.4 A, corresponding to a 2-kV human-body-model (HBM) ESD protection level with a noise figure (NF) of 6.6 dB and a peak gain of 16.5 dB at 60 GHz under a power consumption of only 28 mW.

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (Vt1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (CESD) of 150 fF and prompt response to very fast ESD pulses with rising time (tr) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m2.

Robust ESD protection for high brightness GaN LEDs using new TVS Zener diodes

The electrostatic discharge (ESD) stability of GaN-based LEDs, which are assembled with new transient voltage suppression (TVS) Zener diodes, has been characterized in experiments on reverse leakage current and functionality. Advantageous features of TVS Zener diodes with extremely low differential resistance and low leakage current have enhanced their ESD protection capability, especially at high temperature. The TVS Zener presented an excellent performance in protecting GaN-based LEDs from ESD stress exceeding the human body model ±8 kV at 110 °C. The ESD robustness of the high-temperature stability is analyzed in order to provide proper reliability under hostile environment of massive heat and light delivered from LEDs.

1 fF ESD protection device for gigahertz high-frequency output ESD protection

A mutual-protection scheme is proposed to achieve an ultra-low capacitance electrostatic discharge (ESD) protection device. The ESD protection device can not only dissipate ESD current, but also can make the vulnerable output transistor have the ESD protection capability. Namely, the output transistor can also protect ICs and help the ESD protection device to share the ESD current. Using this scheme can discharge more ESD current than the summation current of the two individual devices. From the ESD test result, it can achieve the required ESD level by using the ultra-low capacitance ESD protection device (∼1.2 fF).

Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology

This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.