Electrostatic Discharge Diodes Research Articles

87‐1: A Study on the Optimal Design of ESD Protection Circuit in OLED Panel Using Electromagnetic Simulation

In the display industry, in line with the high performance and miniaturization of products, the fine patterning and the increase in integration in the backplane process are becoming very important. It is the Electrostatic Discharge (ESD) issue that is increased importance in such a display panel development environment. Careful ESD management is very important because various types of electrostatic issues arising from the panel production process are directly connected to the decline in product quality and productivity. In this paper, we introduce the case of ESD defects in the ESD diode protection circuit of display panels being developed. The ESD failure caused by plasma ions and external surges during fabrication process was identified, and the charge and current path were verified through static and transient simulation to determine how it affects the actual display OLED panel. In addition, the design of ESD diode protection circuits optimized for ESD to robust layout was proposed. As a result, it was possible to reduce electric‐field, an insulating breakdown factor, by more than 80%.

RC-diode ESD protection design for high-frequency applications

To offer the electrostatic discharge (ESD) protection in high-frequency integrated circuits, a new RC-diode ESD protection design is presented in this work. The protection circuit combines the ESD diodes with the embedded silicon-controlled rectifier (SCR) and the inserting resistors to provide the appropriate performances including ESD-current-handling ability, signal loss, and layout area. Based on the experimental results in CMOS chip, the new design is a proper solution for ESD protection in high-frequency applications.

Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level

In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

Design of a bulk-isolated bandgap reference with 3.7 ppm/°C TC in 0.35-μm triple-well CMOS process

ABSTRACTA bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad.

Study on ESD Effects of GaAs HBT Power Amplifiers for DCS/GSM Dual Band Handsets

Study on electrostatic discharge (ESD) impact on the GaAs HBT power amplifier (PA) in DCS/GSM dual band handsets is performed in this paper, which has been regarded as its main reliability issue accounting for most failures of radio frequency integrated circuits. In order to suppress the positive ESD impact on the PA in an effective but very economic way, a set of forward ESD diodes at its input port is replaced by the PN junction of GaAs HBT transistor in its first-stage. Alternatively, to introduce a set of thin film resistors (TFRs) at the front of a HBT transistor is necessary for improving the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> -parameter and stability of PA; however, their electrothermal breakdown possibilities do exist. Therefore, both performance degradation and breakdown events of several PA dies are measured for different ESD voltages described by the human body model, with different TFRs chosen for both DCS and GSM bands, respectively. Their transient temperature responses are also captured and compared for different ESD waveforms, which are predicted using the in-house developed algorithm based on the hybrid time-domain finite-element method.

Electrostatic discharge protection devices with series connection using distributed cell‐based diodes

A series electrostatic discharge (ESD) diode structure is proposed to minimise the degradation induced by thermal interaction between series connected diodes. The proposed series diode is constructed using a distributed cell-based ESD diode. To verify the feasibility of the proposed structure, single and series diodes are designed using the typical and the proposed structures. From the experimental results, it is proved that the ESD survival levels of the proposed series diode are nearly identical to those of the single diode, unlike the case of typical series diodes.

Electro-Static Discharge Protection Design for V-Band Low-Noise Amplifier Using Radio Frequency Junction Varactor

The RF junction varactors are employed as electro-static discharge (ESD) protection devices and co-designed with 60 GHz low-noise amplifier (LNA) fabricated in a 65-nm CMOS technology. The junction varactor acts as an ESD diode to bypass ESD current during ESD zapping, and also utilized as a capacitor to be a part of input matching network of the LNA in normal RF operation. By transmission line pulse (TLP) measurement, the ESD protection capabilities of RF junction varactors are characterized with different device parameters. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD levels to parasitic capacitances (VESD/CESD). With ESD/matching co-design methodology, the ESD-protected LNA demonstrates a second breakdown current It2 of 1.4 A, corresponding to a 2-kV human-body-model (HBM) ESD protection level with a noise figure (NF) of 6.6 dB and a peak gain of 16.5 dB at 60 GHz under a power consumption of only 28 mW.

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of ESD protection diodes have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the FOMs (RON*CESD, ICP/CESD, VHBM/CESD, and ICP/ALayout) of ESD protection diodes with new proposed layout styles can be successfully improved.

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.

A Packaged and ESD-Protected Inductorless 0.1–8 GHz Wideband CMOS LNA

In this letter, an inductorless 0.1-8 GHz wideband CMOS differential low noise amplifier (LNA) based on a modified resistive feedback topology is proposed. Without using any passive inductors, the modified resistive feedback technique implemented with a parallel R-C feedback, an active inductor load, and neutralization capacitors achieves high gain, low noise, and good return loss over a wide bandwidth. To ensure the robustness in the system integration, electro-static discharge diodes are added to the radio frequency pads. The LNA was fabricated using a digital 90 nm CMOS technology. It achieves a 3 dB bandwidth of 8 GHz with a 16 dB voltage gain, noise figures from 3.4 dB to 5.8 dB across the whole band, and an input third-order intermodulation product (IIP3) of -9 dBm. The active area of the chip is 0.034 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The chip was packaged and tested on an FR4 PCB using the chip-on-board approach.

Improved Reliability and ESD Characteristics of Flip-Chip GaN-Based LEDs With Internal Inverse-Parallel Protection Diodes

In this letter, a GaN/sapphire light-emitting diode (LED) structure was designed with improved electrostatic discharge (ESD) performance through the use of a shunt GaN ESD diode connected in inverse-parallel to the GaN LED. Thus, electrostatic charge can be discharged from the GaN LED through the shunt diode. We found that the ESD withstanding capability of GaN/sapphire LEDs incorporating this ESD-protection feature could be increased from several hundreds up to 3500 V in the human body model. Furthermore, flip-chip (FC) technology was also used to produce ESD-protected LEDs to further improve light output power and reliability. At a 20-mA current injection, the output power of the FC LEDs showed an improvement of around 60%. After a 1200-h aging test, the luminous intensities of the FC LEDs featuring an internal ESD-protection diode decreased by 4%. This decay percentage was far less than those of non-FC LEDs

ESD protection structure qualification – a new approach for release for automotive applications

To protect semiconductor products against damages due to electrostatic discharges separate protection structures are necessary. These structures are part of the device pad circuitry and designed for a dedicated wafer technology and ESD ( Electrostatic Discharge) withstanding voltage. All present automotive qualification standards AEC-Q100/101 ( Automotive Electronic Council) [1,2] do not cover a qualification and release of ESD protection structures related to their designed ESD strength. The paper will introduce a new qualification strategy for ESD protection structures depending on the designed ESD target. On dedicated ESD diodes drifts of several parameters versus time were analyzed. The results will be presented and discussed. Release targets for automotive applications will be defined.

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

A new design on the electrostatic discharge (ESD) protection scheme for CMOS IC operating in power-down-mode condition is proposed. By adding a VDD_ESD bus line and diodes, the new proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. Experimental results have verified that the human-body-model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-μm silicided CMOS process. Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition.

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25-/spl mu/m CMOS process to sustain a human-body-model ESD level of greater than 8 kV.

Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.

The impact of MOSFET technology evolution and scaling on electrostatic discharge protection

MOSFET (metal-oxide silicon field effect transistor) evolution and technology scaling impacts electrostatic discharge (ESD) protection networks, design and strategy. The continous evolution of semiconductor processing forces new issues to arise for each technology generation and the evolution of MOSFET structures in each generation requires re-addressing of the scaling implications on ESD robustness. This paper addresses the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness. The scaling of the epitaxial film thickness and p++ vs p− substrate influences the ESD robustness of n-channel MOSFET and diode-based ESD protection networks. ESD diode elements show a 2× to 3× improvement in thin p− epitaxy on a p++ wafer compared to p−substrates. The evolution from diffused wells to MeV-implanted retrograde well designs have shown that the parasitic vertical bipolar transistor plays a lesser role in ESD protection networks compared to the diode action. A 3× HBM (human body model) ESD improvement is demonstrated using advanced high dose MeV retrograde well implants. Isolation technology has an influence on the high voltage electrical parametrics, lateral parasitics, thermal transport and semiconductor process integration with the MOSFET junction and silicide film. The transition from LOCOS to STI (shallow trench isolation) significantly altered the electrical parametrics, failure mechanisms, and ESD networks. The MOSFET-junction evolution from Ldd, dual-Ldd, abrupt junctions to “extension implants” and how this influenced integration and ESD robustness is discussed. MOSFET junctions, salicide, and STI integration issues, such as STI pull-down, can influence the ESD robustness of ESD diode structures. Althernative salicide processes (e.g. cobalt), deep B11 implants and novel poly-silicon-bound diode structures demonstrate 3× improvement in HBM ESD robustness. As technology transitions from aluminum- to copper-based interconnect systems, interconnect wire (2× improvement) and via (3× improvement) ESD improvements are demonstrated. As a result of power supply scaling, the impact of technology scaling on ESD networks, peripheral I/O driver circuits and receiver networks, and how it influences the ESD protection of advanced semiconductor chips is shown. Power-supply scaling, noise issues and multichip systems has led to increasing complexity and importance of sequence-independent ESD networks, ESD networks between power supplies and ESD power clamps. Receiver and I/O driver designs have also evolved due to the MOSFET dielectric scaling and ESD robustness requirements. Technology generation evolution of peripheral driver circuits evolution demonstrates the need for local resistor ballasting of driver circuits. With MOSFET scaling, receiver circuit pass transistors, keeper feedback and zero-Vt devices introduce new ESD issues and receiver design complexity. MOSFET scaling requires ESD power clamps across core and peripheral supplies to reduce the current loop impedance for high frequency applications. MOSFET scaling also has led technology to have a future interest in high-frequency semiconductor devices, such as rf-CMOS, silicon-on-insulator, and SiGe-based devices. Novel SOI ESD networks, such as polysilicon-bound diodes and body- and gate-coupled SOI ESD networks, demonstrate excellent ESD results in advanced CMOS-on-SOI technologies.