Electroplated Copper Interconnects Research Articles

The Influence of Leveler on the Impurity Behavior of Electroplated Cu Films During Laser Annealing

Leveler is one of the key factors for the fabrication of electroplated Cu with superior electrical properties in Cu interconnect metallization. Rarely notice has been paid on the influence of leveler on the impurity behavior of electroplated Cu during recrystallization. In this study, the impacts of five different levelers on the impurity behavior during recrystallization of the electrochemical deposited Cu films are studied in terms of microstructure and electrochemical behavior. Five levelers perform differences in molecular types and inhibition ability on Cu deposition. The former will affect the initial impurity content of the original crystal, while the latter is directly related to the amount of impurity diffusion during recrystallization. This study shows the direct evidence that two factors affect the impurity behavior of the electroplated Cu films during laser annealing and thus affect the resistance performance. We find that the films obtained by using leveler that has a reasonable inhibitory ability and incorporates the lowest initial impurity content shows the largest resistance drop during recrystallization. We believe the findings are meaningful for the selection of levelers to improve electrical property in the metallization of electroplated copper interconnects.

Impurity diffusion behavior study of electroplated copper films annealed by linear shaping laser mobile scanning system

Impurities due to additives in electroplated copper interconnects diffuse during grain growth. High-resolution electron backscatter diffraction and TOF-SIMS (Time-of-flight secondary ion mass spectrometer) results reveal that the electroplated copper films after laser annealing by linear shaping laser mobile scanning system (LALS) have higher recrystallization fraction and less impurity content than traditional thermal annealing. Impurity diffusion behavior and grain boundary migration are inseparable. The effect of LALS on the impurity diffusion of electroplated Cu films is the result of the introduced local temperature gradient, which works collaboratively on the thermodynamics and kinetics of grain boundary migration. And the amount of impurity diffusion is related to the proportion of different species of impurities. The findings are meaningful for the metallization of electroplated copper interconnects.

PS0019-272 薄膜配線長期信頼性に及ぼす微視組織の影響

In this study, the dominant diffusion path in the electroplated copper interconnections used for TSV (through silicon vais) was investigated in detail under the EM (Electromigration) load. The micro texture of the interconnection was analyzed by using an EBSD (Electron Back-scattered Diffraction) method. There were two dominant diffusion paths: the interfaces and random grain boundaries formed at the center of the interconnection. Both paths consisted of porous random grain boundaries with low crystallinity. The random grain boundaries at the center of the interconnection remained even after the annealing at 400℃. Therefore, it is necessary to improve the crystallinity of the as-electroplated film to improve the EM resistance of the electroplated interconnections.

Void control during plating process and thermal annealing of through-mask electroplated copper interconnects

The quality of the sputtered copper film, which serves as the seed layer for sequent electroplating, becomes critical when the size of crack on the surface of the sputtered film is close to the feature size of the electroplated copper interconnect. The crack results in void formation in electroplated copper before thermal annealing and this phenomenon limits attainable highest anneal temperature. To solve this problem, the sputtered seed layer was slightly etched before electroplating process and a TaN passivation layer was deposited on the electroplated Cu interconnect before thermal annealing. Those processes not only suppressed void formation during the electroplating and annealing process at 300°C, but also resulted in lower electrical resistance in the copper interconnects.

PS10 薄膜銅配線の結晶粒界強度の経時劣化測定

Electric and mechanical properties of the electroplated copper thin film interconnections vary drastically depending on not only the size of grains but also the crystallographic characteristics of grain boundaries. In particular, the effect of the quality of grain boundaries plays very important role on the physical properties when the volume ratio of grain boundaries increases with the decrease of average grain size. In this study, in order to evaluate the damage due to the electro migration (EM) of electroplated copper interconnections, the tensile strength at grain boundaries in the interconnection was measured by the micro-tensile test method using Focused Ion Beam (FIB) technique. The micro-texture dependence of the tensile strength and the change in the strength of electroplated copper thin-film interconnections after the EM test were evaluated quantitatively.

PS11 めっき銅薄膜配線の機械特性の多様性

PS11 めっき銅薄膜配線の機械特性の多様性

J061031 半導体薄膜配線材料のナノスケール結晶品質の評価に基づく信頼性設計

With the high integration and the high speed operation of LSIs in recent years, interconnection material has rapidly changed over from conventionally used aluminum alloy to electroplated copper to improve the elevtronic performance of the LSIs. However, it was found that both the electronic characteristics and reliability of th electroplated copper thin films were rather low comparing with those of bulk copper. In this study, the authors clarified that the degradation of the electronic performance of the electroplated copper interconnections is caused by low crystallinity of the interconnectins and the grain boundary diffusion in the films is accelerated by the low crystallinity. The change of the crystallinity was observed by using an EBSD (Electron Back-scattered Diffraction) method. It was found that the crystallinity of the interconnection varied drastically depending on the electroplating conditions and seed layer material. Based on the results, the authors proposed a new design guideline for highly reliabile electroplated copper thin film interconnections.

Mechanical and Electrical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection

AbstractMicro-texture dependence of both the mechanical and electrical properties of electroplated copper thin films was discussed experimentally considering the change of their micro texture caused by thermal history after the electroplating. Both the static and fatigue strength of the films changed drastically depending on the micro texture and it was found that there were two fatigue fracture modes in the films. One was a typical ductile intragranular fracture and the other was brittle intergranular one. The reason for the variation of the strength of the electroplated copper thin films was attributed to the variation of the average grain size and the characteristics of grain boundaries. In addition, the electrical reliability of the electroplated copper interconnections was discussed under electromigration tests. Though abrupt fracture mode due to the local fusion appeared in the as-electroplated films, the life of the interconnections was improved significantly after the annealing at temperatures high than 200°C. Typical change of the surface morphology of the film, i.e., the formation of voids and hillocks were observed on their surfaces after the annealing. This was also caused by the change of the micro texture from fine grains with porous grain boundaries to coarsened columnar grains with rigid grain boundaries. However, the stress-induced migration appeared in the annealed narrow interconnections, in particular. This was because of high tensile residual stress occurred in the film due to the constraint of the shrinkage of the films by rigid oxide around them. These results clearly indicated that the control of both the micro-texture and residual stress is indispensable for improving the reliability of the interconnectins.

Mechanical and microstructural characterization of high aspect ratio through-wafer electroplated copper interconnects

In this paper we present the mechanical and microstructural characterization results of through-wafer electroplated copper interconnects. Copper was deposited in very high aspect ratio (∼15), narrow (15 µm) through-vias in silicon, which were earlier created by deep reactive ion etching. The two critical mechanical properties, i.e. hardness and modulus of elasticity, and the microstructure of the electroplated copper interconnect were determined by nanoindentation, atomic force microscope and x-ray diffraction techniques. A location-dependent hardness characteristic was shown along the length of electroplated copper interconnects. The modulus and the hardness of copper interconnects at the bottom segment (124 GPa and 1.8 GPa) were found to be higher than those at the top segment (116 GPa and 1.1 GPa). The reason behind these variable hardness values in the copper interconnect was due to the different grain sizes and the microstructure in the electroplated copper. These varying grain sizes were caused by the incremental current densities used during electrodeposition. The thermal strain, generated due to the coefficient of thermal expansion mismatch, was measured by the digital image speckle correlation technique. From the results, the thermal strain in the Y-direction was found to be more dominant than that in the X-direction. The grain sizes and the preferred texture orientation in the electroplated copper were characterized by the x-ray diffraction technique.

Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating

In this paper, we report the fabrication of high aspect ratio, highly dense, very fine pitch on-chip copper-pillar-based interconnects for advanced packaging applications. Photoresist molds up to a thickness of 80 µm and having feature sizes as small as 5 µm were fabricated using multi-step coating of the positive tone AZ9260 photoresist. Spin coating and lithography parameters were optimized to achieve smooth and vertical sidewalls. Copper interconnects having an aspect ratio up to 6 and a pitch size of 25 µm were electroplated in the fabricated resist mold. Due to a very small pitch size, the total number of interconnects per cm2 chip area is 160 000, which is much larger than the conventional solder-based interconnects. The electrical resistance of the electroplated copper interconnects was measured by 4-probe kelvin measurement configuration and was found to be in the range of 8–10 mΩ and the corresponding electrical resistivity was calculated as 2.4 µΩ cm. Such low resistive interconnects can carry much larger electrical current without significant electrical loss, which is ideally suitable for next generation packaging applications. X-ray diffraction has shown the presence of the (2 2 0) texture along the length of electroplated copper pillars. Transmission electron microscope reveals the presence of nanoscale copper twins along the length of copper interconnects.

Evolution of Grain and Micro-Void Structure in Electroplated Copper Interconnects

A detailed investigation has been carried out into the evolution of grain size and grain orientation in electroplated Cu interconnection lines. The specimens were annealed to produce a range of different grain size distributions. Very accurate grain size distributions were obtained from extensive TEM observations of a large number of specimens, followed by computer tracing of grain boundaries. Although annealing causes the average grain size to increase, very small grains are found to persist in the distribution, even when the average grain size is large. These small grains have been investigated in detail to determine the reason for their thermal stability. In addition, the occurrence and redistribution of small micro-voids has been investigated for wafers with different grain sizes. These voids are believed to be associated with seams which are formed in the Cu lines during plating.

Microtexture and Strain in Electroplated Copper Interconnects

AbstractThe microstructure of narrow metal conductors in the electrical interconnections on IC chips has often been identified as of major importance in the reliability of these devices. The stresses and stress gradients that develop in the conductors as a result of thermal expansion differences in the materials and of electromigration at high current densities are believed to be strongly dependent on the details of the grain structure. The present work discusses new techniques based on microbeam x-ray diffraction (MBXRD) that have enabled measurement not only of the microstructure of totally encapsulated conductors but also of the local stresses in them on a micron and submicron scale. White x-rays from the Advanced Light Source were focused to a micron spot size by Kirkpatrick-Baez mirrors. The sample was stepped under the micro-beam and Laue images obtained at each sample location using a CCD area detector. Microstructure and local strain were deduced from these images. Cu lines with widths ranging from 0.8 [.proportional]m to 5 [.proportional]m and thickness of 1 [.proportional]m were investigated. Comparisons are made between the capabilities of MBXRD and the well established techniques of broad beam XRD, electron back scatter diffraction (EBSD) and focused ion beam imagining (FIB).