Electronics ASIC Research Articles

The ATLAS RPC Phase-II upgrade for High Luminosity LHC era

Resistive Plate Chambers (RPC) detectors play a crucial role in triggering events containing muons in the central region of ATLAS. In view of the High Luminosity-LHC program, the existing RPC system, consisting of six independent cylindrical detector layers each providing a full space time localization of hits, is currently undergoing a significant upgrade. In the next few years, 306 triplets of new generation RPCs will be installed in the innermost region of the ATLAS Muon Barrel Spectrometer, increasing from 6 to 9 the number of tracking layers, doubling the trigger lever arm. This allows a substantial enhancement of the present trigger redundancy, increasing the coverage from 76% to approximately 96%. Fitting new chambers in the narrow space left in ATLAS inner barrel was a challenge, achieved by optimizing RPC materials and thickness, featuring a 1 mm gas gap (instead of 2 mm), and 1.4 mm resistive electrodes (instead of 1.8 mm) while reaching an high rate capability. To achieve such results, a 100 ps precise Time-to-Digital Converter (TDC) has been integrated in the front-end electronics ASIC. The expected time resolution of a single 1 mm RPC gas gap is approximately 300 ps, and the possibility of a stand-alone Time of Flight measurement will have a huge impact on ATLAS searches for massive long-lived particles. An overview and the present status of the ATLAS RPC Phase-II project will be presented.

An Electro-Photonic System for Accelerating Deep Neural Networks

The number of parameters in deep neural networks (DNNs) is scaling at about 5× the rate of Moore’s Law. To sustain this growth, photonic computing is a promising avenue, as it enables higher throughput in dominant general matrix-matrix multiplication (GEMM) operations in DNNs than their electrical counterpart. However, purely photonic systems face several challenges including lack of photonic memory and accumulation of noise. In this article, we present an electro-photonic accelerator, ADEPT, which leverages a photonic computing unit for performing GEMM operations, a vectorized digital electronic application-specific integrated circuits for performing non-GEMM operations, and SRAM arrays for storing DNN parameters and activations. In contrast to prior works in photonic DNN accelerators, we adopt a system-level perspective and show that the gains while large are tempered relative to prior expectations. Our goal is to encourage architects to explore photonic technology in a more pragmatic way considering the system as a whole to understand its general applicability in accelerating today’s DNNs. Our evaluation shows that ADEPT can provide, on average, 5.73× higher throughput per watt compared to the traditional systolic arrays in a full-system, and at least 6.8× and 2.5× better throughput per watt, compared to state-of-the-art electronic and photonic accelerators, respectively.

A high speed frontend electronics ASIC for multi-channel single gap RPC detector

This paper presents a high speed prototype frontend electronics (FEE) ASIC, designed to meet the readout requirements of ∼ 3.6 million channels of avalanche mode single-gap resistive plate chamber detectors of Iron Calorimeter experiment of India based Neutrino Observatory. This ASIC is a regulated cascode transimpedance pre-amplifier based octal amplifier-comparator FEE solution in 0.35 μm CMOS process. Two DC stabilization techniques, one for common mode and another for differential DC offset cancellation, have been incorporated in this ASIC to ensure amplifier baseline stability, uniform dynamic range and comparator overdrive across readout channels. This DC common mode control can also be used to trim the input impedance of regulated cascode pre-amplifier. The ASIC provides parallel LVDS outputs on external 100 Ω load for tracking and precision time-tagging. A multiplexed analog output is also provided through an on-chip 50 Ω cable driver for detector pulse profile analysis. The ASIC has total channel gain of ∼ 0.75 mV/fC for single ended inputs of both the polarities, intrinsic timing precision of ∼ 190 ps RMS and ∼ 100 ps RMS for input charge of 0.1 pC and beyond 0.3 pC respectively with total power consumption of 40 mW/channel.

Investigating microchannel plate PMTs with TOFPET2 multichannel picosecond timing electronics

TOFPET2 is the second-generation design of a high-performance multichannel picosecond timing readout electronics ASIC produced by PETsys Electronics SA, Portugal. Originally developed for time-of-flight positron emission tomography using silicon photomultipliers, in this work we describe an experimental programme to evaluate the performance of TOFPET2 with pixelated microchannel plate (MCP) photomultiplier tube (PMT) detectors.Investigations were performed using various signal input methods; injected electronic stim signals, SiPM photodetectors, a single anode MCP photomultiplier detector and finally imaging with a demountable multi-anode MCP detector using a 16 x 16 pixelated multi-layer ceramic readout. The detector utilised an active anode plus image charge configuration to provide the positive signal pulses required by the electronics.Measurements were undertaken using the PETsys Time-of-Flight ASIC evaluation kit (mark2) operating in single photon counting mode. We present performance results for time resolution, cross channel coincidence time resolution and energy resolution using internal pulse amplitude measurement and time-over-threshold signal paths.Photodetector timing performance was evaluated using a 40 ps wide pulsed laser, operating at single photon level using a temperature stabilised setup within a dark enclosure. Amplitude walk correction was applied using the in-built time-over-threshold output from the TOFPET2 system. Single photon timing resolution of better than 110 FWHM was demonstrated. Preliminary results obtained using signal spread over adjacent pixels of a pixellated anode yield a coincidence timing resolution of ∼87 ps rms.

Design and Implementation of an Integrated Reconfigurable Silicon Photonics Switch Matrix in IRIS Project

This paper aims to present the design and the achieved results on a CMOS electronic and photonic integrated device for low cost, low power, transparent, mass-manufacturable optical switching. An unprecedented number of integrated photonic components (more than 1000), each individually electronically controlled, allows for the realization of a transponder aggregator device which interconnects up to eight transponders to a four direction colorless-directionless-contentionless ROADM. Each direction supports 12 200-GHz spaced wavelengths, which can be independently added or dropped from the network. An electronic ASIC, 3-D integrated on top of the photonic chip, controls the switch fabrics to allow a complete and microsecond fast reconfigurability.

Electrografted P4VP for High Aspect Ratio Copper TSV Insulation in Via-Last Process Flow

Via-Last metallization of High Aspect Ratio Through Silicon Via (HAR TSV) for 3D integration is challenging. Indeed, the formation of a uniform and conformal dielectric to insulate HAR TSVs in Via-Last process flow is difficult to achieve for any physical deposition process. In this study, we present the first reported HAR copper TSVs, insulated by highly conformal electrografted poly-4-vinylpyridine (P4VP) in Via-Last process-flow. As a demonstration, this allowed the metallization of HAR copper TSVs for die-to-die 3D integration of a 22 × 22 photodiode array tier onto a CMOS control electronics ASIC.

Non-invasive characterization and quality assurance of silicon micro-strip detectors using pulsed infrared laser

The Compressed Baryonic Matter (CBM) experiment at FAIR is composed of 8 tracking stations consisting of roughly 1300 double sided silicon micro-strip detectors of 3 different dimensions. For the quality assurance of prototype micro-strip detectors a non-invasive detector charaterization is developed. The test system is using a pulsed infrared laser for charge injection and characterization, called Laser Test System (LTS). The system is aimed to develop a set of characterization procedures which are non-invasive (non-destructive) in nature and could be used for quality assurances of several silicon micro-strip detectors in an efficient, reliable and reproducible way. The procedures developed (as reported here) uses the LTS to scan sensors with a pulsed infra-red laser driven by step motor to determine the charge sharing in-between strips and to measure qualitative uniformity of the sensor response over the whole active area. The prototype detector modules which are tested with the LTS so far have 1024 strips with a pitch of 58 μm on each side. They are read-out using a self-triggering prototype read-out electronic ASIC called n-XYTER. The LTS is designed to measure sensor response in an automatized procedure at several thousand positions across the sensor with focused infra-red laser light (spot size ≈ 12 μm, wavelength = 1060 nm). The pulse with a duration of ≈ 10 ns and power ≈ 5 mW of the laser pulse is selected such, that the absorption of the laser light in the 300 μm thick silicon sensor produces ≈ 24000 electrons, which is similar to the charge created by minimum ionizing particles (MIP) in these sensors. The laser scans different prototype sensors and various non-invasive techniques to determine characteristics of the detector modules for the quality assurance is reported.

Characterization of silicon micro-strip sensors with a pulsed infra-red laser system for the CBM experiment at FAIR

The Compressed Baryonic Matter (CBM) experiment at FAIR is composed of 8 tracking stations consisting of 1292 double sided silicon micro-strip sensors. For the quality assurance of produced prototype sensors a laser test system (LTS) has been developed. The aim of the LTS is to scan sensors with a pulsed infra-red laser driven by step motor to determine the charge sharing in-between strips and to measure qualitative uniformity of the sensor response over the whole active area. The prototype sensors which are tested with the LTS so far have 256 strips with a pitch of 50 μm on each side. They are read-out using a self-triggering prototype read-out electronic ASIC called n-XYTER. The LTS is designed to measure sensor response in an automatized procedure at several thousand positions across the sensor with focused infra-red laser light (spot size ≈ 12 μm , wavelength = 1060 nm). The pulse with duration (≈ 10 ns) and power (≈ 5 mW) of the laser pulses is selected such, that the absorption of the laser light in the 300 μm thick silicon sensors produces a number of about 24000 electrons, which is similar to the charge created by minimum ionizing particles (MIP) in these sensors. Laser scans different prototype sensors is reported.

PARISROC, a photomultiplier array readout chip (PMm2 collaboration)

PARISROC is a complete readout chip, in AMS SiGe 0.35μm technology, for photomultipliers array. It is a front-end electronics ASIC which allows trigerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French National Agency for Research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerless acquisition and only sends out the relevant data by network to the central data storage. This data management reduces considerably the cost of these detectors. This paper describes the front-end electronics ASIC called PARISROC which integrates totally independents 16 channels with a variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.