Electronic System Level Design Flow Research Articles

Towards automated implementation of adaptive systems from abstract SystemC specifications

Adaptivity is a key feature in embedded systems which requires explicit support in Electronic System-Level (ESL) design methodologies. Similarly, a higher level of abstraction during system specification is crucial for enabling ESL design activities such as Design Space Exploration. This has motivated the development of methodologies, such as A-HetSC, for enabling SystemC abstract specification of the adaptive parts of a system. However, in order to enable practical ESL design flows, it is essential to enable suitable implementation paths from the abstract adaptive specification. Otherwise, the cost of manual refinement of the abstract adaptive specification or simply the inability to systematically achieve an implementation will compromise the advantages obtained by the abstract model. This paper presents a system-level implementation methodology for tackling the implementation of the adaptive parts of an abstract SystemC specification. These adaptive parts are described as abstract adaptive processes, the basic constructs for specifying adaptivity in the A-HetSC methodology. The methodology proposes two main implementation paths. One path automatically targets an embedded SW implementation, for an immediate, flexible and cheap implementation of the adaptive processes. For the HW implementation path, a systematic SystemC-based refinement for targeting a refined model is proposed. Such a refined model is already supported by high-level synthesis tools, which automate the rest of the HW implementation path. It enables a cost efficient implementation of adaptive functionality in contexts where a software implementation does not fulfil time performance demands. The refinement of an adaptive inverse transform module, as part of an adaptive video decoder (AVD), is used as a demonstrative example.

A Multi-Granularity Power Modeling Methodology for Embedded Processors

With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on the OpenRISC and MIPS processors demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/instruction set simulator models that can be used in transaction level models, to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development

In this paper, we present a fast cycle-accurate instruction set simulator (CA-ISS) for system-on-chip development based on QEMU and SystemC. Even though most state-of-the-art commercial tools have tried very hard to provide all the levels of details to satisfy the different requirements of the software designer, the hardware designer, and even the system architect, the hardware/software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level (RTL) with a full-fledged operating system (OS). Our experimental results show that the combination of QEMU and SystemC can make the co-simulation at the CA level much faster than the conventional RTL simulation, even with a full-fledged operating system up and running. Furthermore, the statistics indicate that with every instruction executed and every memory accessed since power-on traced at the CA level, it takes 28m15.804s on average to boot up a full-fledged Linux kernel, even on a personal computer. Compared to the kernel boot time reported by Xilinx and SiCortex, the proposed CA-ISS is about 6.09 times faster compared to “SystemC without trace” of Xilinx and about 30.32 times faster compared to “SystemC models converted from RTL” of SiCortex. The main contributions of this paper are threefold: 1) a hardware/software co-simulation environment capable of running a full-fledged OS at the early stage of the electronic system level design flow at an acceptable simulation speed is proposed; 2) a virtual platform constructed using the proposed CA-ISS as the processor model can be used to estimate the performance of a target system from system perspective, which all the previous works, such as QEMU-SystemC, do not provide; and 3) such a virtual platform also provides the modeling capability from the transaction level down to the CA level or the other way around.