Electronic Packaging Structures Research Articles

Enhancement of the Numerical Stability of the Adaptive Integral Method at Low Frequencies Through a Loop-Charge Formulation of the Method-of-Moments Approximation

The performance of integral-equation-based fast iterative solution schemes such as the adaptive integral method (AIM) and the conjugate gradient (CG) fast Fourier transform (FFT) algorithm can be substantially improved at low frequencies if the electric current and electric charge densities are treated as two separate unknown quantities. The representation of the current density in terms of solenoidal expansion functions (loops) and the charge density in terms of pulse basis functions provides for an exact decomposition of the original electromagnetic (EM) boundary-value problem into its magnetostatic and electrostatic forms at zero frequency. This formulation allows for accurate EM modeling down to very low frequencies free of numerical instabilities, while the spectral properties of the matrix equation are substantially improved compared to the standard method of moments formulation in either loop-tree or loop-star basis. The AIM and the CG FFT algorithms can be appropriately adjusted to accommodate for the use of loop-charge basis functions, thus leading to efficient solvers with O(NlogN) solution complexity and O(N) memory requirements for two-and-one-half-dimensional and penetrable three-dimensional (3-D) structures. For general 3-D objects, the CPU time and memory of the algorithms scale as O(N/sup 1.5/logN) and O(N/sup 1.5/), respectively. The new implementation of the AIM is discussed and demonstrated through its application for the broad-band simulation of complex interconnect and electronic packaging structures.

An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

An integrated process modeling methodology using a coupled cure-thermal-stress analysis approach has been developed to determine the evolution of warpage and stresses during the sequential fabrication of high-density electronic packaging structures. The process modeling methodology has been demonstrated, for example, with a bi-layer structure consisting of a 3 mil (76.2 /spl mu/m) thick Vialux 81 photo-definable dry film (PDDF) polymer on a silicon substrate. Extensive material characterization of the thermo-mechanical properties of the thin film polymer is presented, including the development of a viscoelastic material model. The predicted warpage values have been validated with shadow Moire experiments, while the predicted stress values have been validated with experimental data using the Flexus Thin Film Stress Measurement Apparatus. Good agreement is seen between the predicted and the experimental warpage and stress values during the entire cure cycle. Finally, the importance of incorporating viscoelastic polymer behavior and processing history is emphasized in the context of developing the multi-layered high-density wiring integrated substrate fabrication process.

Analysis of interfacial thermal stresses of chip-substrate structure

The interfacial thermal stresses of the chip-substrate structure near free edges play an important role in determining the reliability of electronic packaging structures. According to the heat conduction mechanism of integrated circuits, the temperature field of the chip and the substrate is derived when the chip works in a steady state. A simple method is developed to determine the stress field of the chip and the substrate, which can exactly satisfy the traction-free boundary conditions and continuity conditions on the interface. The corresponding stress field is solved in terms of the variational principle. Finally, the effect of geometrical parameters of the chip and the substrate on stress concentration is analyzed in detail.

Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling

Components in electronic packaging structures are of different dimensions and are made of dissimilar materials that typically have time, temperature, and direction-dependent thermo-mechanical properties. Due to the complexity in geometry, material behavior, and thermal loading patterns, finite-element analysis (FEA) is often used to study the thermo-mechanical behavior of electronic packaging structures. For computational reasons, researchers often use two-dimensional (2D) models instead of three-dimensional (3D) models. Although 2D models are computationally efficient, they could provide misleading results, particularly under thermal loading. The focus of this paper is to compare the results from various 2D, 3D, and generalized plane-deformation strip models and recommend a suitable modeling procedure. Particular emphasis is placed to understand how the third-direction coefficient of thermal expansion (CTE) influences the warpage and the stress results predicted by 2D models under thermal loading. It is seen that the generalized plane-deformation strip models are the best compromise between the 2D and 3D models. Suitable analytical formulations have also been developed to corroborate the findings from the study. [S1043-7398(00)01402-X]

Closed form vs. finite element analysis of laminated stacks

Recently, structural analysis of multi-layered stacks subjected to thermal loading has received considerable renewed interest. This is partly because of popular use of these structures in electronic packaging. In this paper a comparative analysis of these structures is presented. Comparisons between closed-form solution, elastic, viscoplastic and thermo-viscoplastic with damage analyses have been presented. A damage mechanics based constitutive model is proposed for finite element analysis (FEA) of multi-layered structures. Moreover, mesh sensitivity of the FEA in layered stack problems is studied. It is shown that the closed-form and elastic FEA can only be used for preliminary studies and elastic finite element method is highly mesh sensitive for this problem. In elastic analysis the stress singularity at the free edge makes mesh selection very difficult. On the other hand, inelastic analysis does not suffer from the stress singularity problem encountered in elastic analysis. The damage mechanics based constitutive model proposed in the study uses a thermodynamic internal state variable as a damage metric.

Visualization of Three-Dimensional Delaunay Meshes

We describe an algorithm for the rapid display of three-dimensional Delaunay meshes (or selected portions thereof) on standard raster displays, without the use of special purpose graphics hardware. The algorithm allows the display of the interior structure as well as the surface of the mesh, and furthermore does not require that the meshed domain be convex, or even connected. The algorithm computes a depth ordering on the mesh elements. This ordering can be used to display subsets of the mesh, as well as isosurfaces induced by fields represented on the mesh. Furthermore, by utilizing mesh coherence, the depth ordering can be used to view the mesh from front to back as well as back to front. An implementation of the algorithm has been incorporated in a system for designing and analyzing the performance of three-dimensional semiconductor and electronic packaging structures. The system is in regular use and the mesh-display algorithm has been used to visualize both meshes and fields computed over the meshes.

A novel thick-film technique, gravure offset printing, for the realization of fine-line sensor structures

Gravure offset printing is a novel thick-film printing technique which offers the possibility of printing conductor lines that are narrow compared with those obtained by screen-printing technology. Therefore by using gravure offset printing, denser electronic packaging and sensor structures are feasible. This paper reports the line width and thickness of conductors on alumina substrates produced by the gravure offset technique. As an application example, a multilayer pressure sensor structure consisting of 64 sensors, each 2×2 mm 2 in size, in a matrix is described. This structure is composed of two electrode layers with a piezoceramic layer between them. The narrowest line width of the electrodes is 50 μm. One of the most important benefits of this technique is that it offers the possibility of three-dimensional printing.

4855867 Full panel electronic packaging structure

4855867 Full panel electronic packaging structure

Analytical Modeling in Electronic Packaging Structures: Its Merits, Shortcomings and Interaction With Experimental and Numerical Techniques

We discuss the role of theoretical and, in particular, analytical modeling in mechanical problems for electronic packaging, including requirements for a feasible theoretical model, how such a model is developed, the role of mathematics, what can be gained by using theoretical modeling, as well as the interaction of analytical, numerical (computer-aided) and experimental models. Peculiarities of theoretical modeling in Structural Analysis are also briefly discussed.

4766670 Full panel electronic packaging structure and method of making same

4766670 Full panel electronic packaging structure and method of making same

Characteristics of Coupled Buried Microstrip Lines by Modeling and Simulation

Electrical characteristics of coupled buried microstrip lines were obtained using a recently developed two-dimensional TEM transmission line parameter modeling tool. The capacitance [C] and inductance matrix [L] parameters were used in a lossless TEM mode transmission line transient response calculator to determine the maximum coupled noise. It is found that there is a critical depth of bury h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> below which the lines appear to be within an infinite dielectric and above which there is coupling to the polarization charge on the dielectric interface. This often results in very complicated Coupled noise behavior as the coupling of the lines is capacitive at One depth of bury and inductive at another depth of bury. Parameter simulation and maximum noise results are given for a wide variety of structures important in integrated circuit electronic packaging structures.