Electronic Design Automation Software Research Articles

A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses

Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells.

Enhancing Electronic Design Automation Tools with an ML-Based Information Retrieval System

Over the past fifty years, Electronic Design Automation (EDA) tools have played a crucial role in the semiconductor industry, assisting in the design, simulation, and manufacturing of integrated circuits (ICs). However, the sophisticated nature of these tools often demands extensive expertise, which can be a barrier for many users. Mastery of these tools necessitates specialized knowledge and skills, including comprehension of complex algorithms, design methodologies, and tool-specific workflows. To address this challenge, this paper introduces a machine learning (ML) based information retrieval system designed to enhance the usability of EDA tools. The objective of this system is to simplify user interactions and make EDA tools more accessible to designers, regardless of their expertise level. The main idea of this ML-driven system is to provide a chatbot-like interface that facilitates efficient, context-aware searches and offers interactive, step-by-step guidance on using various tool functionalities. By integrating natural language processing and machine learning techniques, the system can understand user queries, extract relevant information from the tool's documentation, and provide context-specific guidance. This approach helps to mitigate the steep learning curve associated with advanced EDA applications and enhances tool accessibility. Consequently, it promotes a more intuitive interaction with sophisticated EDA software, thus fostering enhanced usability of complex tools in the semiconductor industry. This work exemplifies the transformative potential of integrating machine learning with conversational user interfaces in making sophisticated software applications more user-friendly.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

DeltaLCA

Reducing the environmental footprint of electronics and computing devices requires new tools that empower designers to make informed decisions about sustainability during the design process itself. This is not possible with current tools for life cycle assessment (LCA) which require substantial domain expertise and time to evaluate the numerous chips and other components that make up a device. We observe first that informed decision-making does not require absolute metrics and can instead be done by comparing designs. Second, we can use domain-specific heuristics to perform these comparisons. We combine these insights to develop DeltaLCA, an open-source interactive design tool that addresses the dual challenges of automating life cycle inventory generation and data availability by performing comparative analyses of electronics designs. Users can upload standard design files from Electronic Design Automation (EDA) software and the tool will guide them through determining which one has greater carbon footprints. DeltaLCA leverages electronics-specific LCA datasets and heuristics and tries to automatically rank the two designs, prompting users to provide additional information only when necessary. We show through case studies DeltaLCA achieves the same result as evaluating full LCAs, and that it accelerates LCA comparisons from eight expert-hours to a single click for devices with ~30 components, and 15 minutes for more complex devices with ~100 components.

A comparative analysis of traditional and AI-based routing algorithms in electronic design automation

Rapid advances in artificial intelligence (AI) and machine learning have had a significant impact on various fields, including electronic design automation (EDA). This study aims to compare current EDA routing algorithms with AI-based routing algorithms, highlighting their respective advantages and limitations. Through a comprehensive analysis of existing EDA routing algorithms and artificial intelligence-based technologies, this study explores the applicability of these algorithms in different EDA scenarios, with a focus on their effectiveness and efficiency in routing tasks, and aims to compare and contrast traditional and AI-based routing algorithms in the context of electronic design automation. It also shows that the current AI technology will play an important role in the future development of EDA software. Therefore, the combination of AI technology may be the focus of EDA software development, so as to help elucidate the evolving landscape of EDA and provide insights into the potential future direction, and provide a a comprehensive understanding of their underlying methodologies, advantages, and limitations of traditional and AI-based algorithms in the context of electronic design automation.

Design of Full Swing Carry Generator Using Mentor Graphics

Abstract: A Full adder is built specifically for creating full-swing carry output utilizing Mentor graphics in this project. Mentor Graphics is electronic design automation software that is used to create superior electronic devices more quickly and costeffectively. The proposed circuit, which has a high driving capability, is suitable for a wide range of multistage structure applications. In digital processing equipment, full adders are used for multiple adders. This circuit design employs a unique mode to provide a full swing carry output, and its performance is governed by suitable inputs, static power reduction, and transistor series construction. The full adder proposed here is an efficient gate for Integrated Circuits (ICs). The performance between simulation and measurement produced a very good approximation result. When compared to other circuits, the cell's performance under variations indicates its excellent driving capabilities while consuming very little power and PDP. The circuit makes use of a one-of-a-kind module to provide full-swing Carry output, and its performance is governed by appropriate inputs, static power reduction, and transistor series formations.

Simulated Annealing Particle Swarm Optimization for a Dual-Input Broadband GaN Doherty Like Load-Modulated Balance Amplifier Design

In this brief, an automatic power amplifier (PA) design system based on simulated annealing particle swarm optimization (SA-PSO) algorithm is proposed to perform multi-objective optimization in designing broadband Doherty like load-modulated balanced amplifier (LMBA). Specifically, by combining the programming environment with commercial electronic design automation (EDA) software, the optimization process can be implemented automatically. Then, complex and rigorous impedance trajectory aligning at different power levels can be easily obtained using the proposed optimization algorithm, demonstrating the automatic PA design system’s superiority over the built-in optimizer in commercial EDA software for designing broadband Doherty like LMBA. A 2.5-3.5 GHz dual-input Doherty like LMBA is simulated and measured, showing a saturated output power of 45.4-48.2 dBm, a saturation drain efficiency of 60.7% - 69.7%, a 6 dB power back-off DE of 59.2% - 65.8%, and a 9 dB power back-off DE of 52.7% - 66.9%.

China’s Counter-Strategy to American Export Controls in Integrated Circuits

This article examines China’s efforts to counter American sanctions against Huawei that in effect try to weaponize the silicon supply chain. While China has taken tentative steps to try to decouple from the American semiconductor industry, it faces three continuing challenges. First, the areas of technological dependence that the Huawei Entity List sanctions highlighted, fabrication capital equipment and electronic design automation (EDA) software, are areas in which China has very weak capabilities. Second, the wider the scope of the sanctions is, the more likely local and foreign firms will be willing to cooperate with Chinese efforts to create substitutes for controlled American technologies. But the scope of the sanctions appears to be in stasis and may even narrow during the Biden administration. Finally, the progressive expansion of China’s silicon ambitions has elicited foreign industrial policies to counter China’s own policies. This expanding market outside of China will lessen the effectiveness of Chinese policy and at the same time make a certain level of controls over IC technology palatable to American partners as Chinese customers are replaced by others.

Broadband Lumped-Element Parameter Extraction Method of Two-Port 3D MEMS In-Chip Solenoid Inductors Based on a Physics-Based Equivalent Circuit Model.

Integrated 2D spiral inductors possess low inductance per unit area, which limits their application range. However, the state of investigation into the lumped-element parameter extraction method for integrated 3D in-chip multi-turn solenoid inductors, which possess higher inductance per unit area, is inadequate. This type of inductor can thus not be incorporated into fast computer-aided design (CAD)-assisted circuit design. In this study, we propose a broadband two-port physics-based equivalent circuit model for 3D microelectromechanical system (MEMS) in-chip solenoid inductors that are embedded in silicon substrates. The circuit model was composed of lumped elements with specific physical meanings and incorporated complicated parasitics resulting from eddy currents, skin effects, and proximity effects. Based on this model, we presented a lumped-element parameter extraction method using the electronic design automation software package, Agilent Advanced Design System (ADS). This method proved to be consistent with the results of two-port testing at low to self-resonant frequencies and could thus be used in CAD-assisted circuit design. The lumped element value variations were analyzed based on the physical meaning of the elements with respect to variations in structures and the substrate resistivity of inductors. This provided a novel perspective in terms of the design of integrated in-chip solenoid inductors.

Sensing Features of the Fano Resonance in an MIM Waveguide Coupled with an Elliptical Ring Resonant Cavity

In this article, a novel refractive index sensor composed of a metal–insulator–metal (MIM) waveguide with two rectangular stubs coupled with an elliptical ring resonator is proposed, the geometric parameters of which are controlled at a few hundreds of nanometer size. The transmission feature of the structure was studied by the finite element method based on electronic design automation (EDA) software COMSOL Multiphysics 5.4 (Stockholm, Sweden). The rectangular stub resonator can be thought of as a Fabry–Perot (FP) cavity, which can facilitate the Fano resonance. The simulation results reveal that the structure has a symmetric Lorentzian resonance, as well as an ultrasharp and asymmetrical Fano resonance. By adjusting the geometrical parameters, the sensitivity and figure of merit (FOM) of the structure can be optimized flexibly. After adjustments and optimization, the maximum sensitivity can reach up to 1550 nm/RIU (nanometer/Refractive Index Unit) and its FOM is 43.05. This structure presented in this article also has a promising application in highly integrated medical optical sensors to detect the concentration of hemoglobin and monitor body health.

Electronic Design Automation tools for superconducting circuits

Superconducting integrated circuits have long been completely handcrafted or at best designed with a loose collection of tools that require manual manipulation of data and design transfer between tools. Electronic Design Automation (EDA) software development requires significant investment of resources to track the evolution of integrated circuit fabrication processes, which has only been possible commercially for highly successful semiconductor integrated circuit processes. The IARPA SuperTools project which started in 2017 is the largest known investment to date made in superconducting EDA tool development. SuperTools is divided into two main categories: high-level tools for the synthesis of digital logic circuits, clock networks and placed-and-routed layouts for systems such as processors with millions of logic gates; and physical-level tools for the design, simulation, optimisation, verification, layout and parameter extraction of devices and digital logic cells with the inclusion of fabrication process simulation. In this paper the modules developed for the ColdFlux project under SuperTools are discussed from device modelling to chip tape-out. Progress on parameter extraction tools is highlighted.

Using Electronic Design Automation and Guided Inquiry Learning Model in Higher Engineering Education

Electronic design automation software is a part of software learning. This study uses digital electronic circuit design software as learning media, namely, Electronic Design Automation (EDA), in the form of simulations and a guided inquiry learning model in higher engineering education. The device is a type of multimedia, because it involves graphics, animation, and text as external data. The software facilitates the learning process of cadets using the guided inquiry learning model. Given its accessibility, mobile learning has its own advantages. This study uses quantitative data with a type of quasi-experimental research. The sample consists of 100 cadets in the engineering study program. Results show that the model can improve the learning process of cadets in the air digital engineering program subject, in which the implementation of the model has been integrated into a special theme from the test scores and results of cadets. An effect is observed on the use of the EDA and guided inquiry model to the learning outcome and motivation of cadets in engineering education. The researchers concluded that the implementation of EDA and the guided inquiry model are effective. In addition, it provides benefits for practitioners and educators in improving the learning outcomes and motivation of cadets in engineering education.

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic refresh cycles, which are determined according to the worst-case data retention time (DRT) across process, voltage and temperature (PVT) variations. Even though several DRT characterization methodologies have been reported in literature, they often require unfeasible run-times for accurate DRT evaluation, or they result in highly pessimistic design margins due to their inaccuracy. In this work, we propose an current-based DRT (IDRT) characterization methodology that enables accurate DRT evaluation across process variations without the need for a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy and run-time across several gain-cell structures at different process technologies, providing less than a 4% DRT error and over $100\times $ shorter run-time compared to a conventional DRT evaluation methodology.

Parametrization of CPW for Photonics Application with the Use of Closed Form Formulas

In this paper parametrized analysis of CPW (Coplanar Waveguide) applied in photonics is presented. The analysis is based on analytical formulas, which were delivered and modified from conformal mapping technique, and also after review of available literature from analytical models for the conventional CPW. Adjustment of the already reported CPW formulas was performed to properly model thin films CPW structures in PIC (Photonic Integrated Circuit). Thus, a closed expressions were proposed to simulate basic parameters, like: per unit length (p.u.l.) R (resistance), L (inductance), C (capacitance), G (conductance) and propagation quantity like characteristic impedance Zo versus frequency. The CPW line dedicated for the PIC application, is based on InP (Indium Phosphide) substrate and with air or BCB (Benzocyclobutene) surroundings of the metallization on the top. The modified formulas are curve-fitting approximations, with new fitting coefficients. Essential modifications are for p.u.l. C and p.u.l. L. Usefulness and effectiveness of the modified method was verified through results comparison with simulations in full-wave Electronic Design Automation software, with the circuit simulator QUCS and with real measurements, conducted with the use of PNA (Performance Network Analyzer). The paper novelty are new coefficients for analytical formulas, implementation of modified formulas in the octave code and model parametrization for geometrical parameters.

Focus on test, measurement, and analytical equipment

Focus on test, measurement, and analytical equipment

Design of Non-Volatile Phase Change Memory for FPGA Architectures

Phase change memory circuit has been designed to function as Non-Volatile memory circuit using 45nm and 90nm technology. The other non-volatile memory circuits like Flash and MTJ-MRAM are realized in 45nm and 90nm CMOS Technology in which their output behavioral characteristics, power and delay parameters are obtained in order to compare with performance of MTJ-MRAM and Flash memory circuits. The design has been carried out using Cadence Virtuoso – Electronic Design Automation (EDA) Software tool in Analog Design Environment (ADE), the advanced design and simulation is performed in virtuoso platform. The schematic for PCM is designed and simulations are carried out in 45nm and 90nm technology using a test environment. Further the work has been extended to design memory circuit that gives non-volatility which can be implemented for FPGA architecture. Existing FPGA architectures which are non-volatile based, have limitations and demands for a better computing memory to be integrated within. The present work brings out a novel Phase Change Memory design with better performance than existing flash based and anti-fuse based types of FPGAs and also better than MTJ-MRAM attributes. The present work compares attributes like power dissipation and delay of PCM with other non volatile memories used for FPGA architecture. Further PCM techniques indicate significant power and delay reduction when compared to MTJ-MRAM and flash memory circuit.

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low-noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two-stage low-noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two-stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre-determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures-of-merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka-band (26.5-31.5 GHz) and K-band (20.0-24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka-band and K-band version. Input and output matching are typically better than 12 and 15 dB.

A new and improved electric fish finder with resources for printed circuit board fabrication

ABSTRACT We describe the circuit design, construction, and operation of a field-portable electric fish finder (an AC-coupled wide-band differential bio-amplifier with loudspeaker output). This device permits detection and monitoring of the electric organ discharges generated by neotropical gymnotiform fishes (as well as the mormyroid fishes of tropical Africa). Our design is modified from earlier versions to optimize detection performance and stability over a wider range of ambient water conductivity, including under conditions of extremely low conductivity (< ca. 10 μScm-1). Our new electric fish finder design also incorporates complete waterproofing and longer battery autonomy. We provide Gerber and Eagle files made with the electronic design automation software ‘Autodesk Eagle’ to allow researchers to order printed circuit boards directly from commercial manufacturers.

Modeling the topography of uneven substrates post spin-coating

The semiconductor industry has followed Moore's law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inverted. However, a more promising approach is to reduce the topography by using a planarizing spin-coating process to fill the patterns. Material vendors and research groups have done tremendous efforts to understand and improve the quality (uniformity, planarity, etch resistance, etc.) of spin-coating processes. When a spin-coating process is used to fill a given patterned structure, it is known that the degree of planarization is impacted by a set of parameters such as pattern width and density. However, it is not clear yet what the exact functional dependence is. In this work, the authors first present an experimental study of the planarization behavior of spin-coated materials as a function of pattern width, depth, and density. The authors observed a strong dependency of the width and the density of the patterns on the wafer topography post spin-coating, while the depth, within the boundaries of this study, showed no significant impact. The most striking result was the observation of the linear relationship between the pattern density difference between two areas and the relative height difference of those areas after spin-coating. Second, based on these experimental observations, the authors present a model that predicts the remaining wafer topography post spin-coating. The model calculates the topography for a given set of structures, using only one parameter as input. This parameter is a fixed number for a specific spin-coating process and is called the planarization length λ. The authors demonstrate that this model is capable of reproducing and predicting the experimentally measured height profiles on complex patterned structures for different spin-coating processes. These calculations can be done with commercially available electronic design automation software. Therefore, this model can become a powerful tool in mask design, both for applications based on tone reversal, and, in general, for patterning processes that make use of spin-coated materials.

Development and Demonstration of Routing and Placement EDA Tools for Large-Scale Adiabatic Quantum-Flux-Parametron Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient superconductor logic due to zero static power dissipation and adiabatic switching operation. However, there is a shortage of electronic design automation (EDA) software tools adaptable to AQFP logic. Such tools are essential for designing large-scale-integration circuits efficiently. Therefore, we have developed a first set of EDA tools that handle cell placement and wiring, written in SKILL, the Cadence scripting language. Our tools also consider the maximum wire length constraint that exists in AQFP logic. First, AQFP logic cells are repositioned via the genetic algorithm to minimize the number of wires that violate the wiring length constraint. Buffers are then automatically inserted as signal repeaters for logic rows where the violations still exist. We then complete the logic wiring of the circuit using the channel routing algorithm. We demonstrate the usability of the EDA tools by designing a 16-bit adder as well as a randomly generated test circuit.