Electronic Design Automation Industry Research Articles

Challenges and opportunities for semiconductor and electronic design automation industry in post-Covid-19 years

The coronavirus pandemic found the semiconductor industry and the chip production supply chain ecosystem unprepared. Companies and main actors in the sector could not read the signs. The decision-makers suffered to deal with the challenges in time and take the right actions. The bullwhip effect caused by the COVID-19 destabilized the operations and some of the experts say that these problems might last and on the other side, this might open doors to innovative solutions that might change the game. The global shutdowns, the misread of the demand for electronics, underestimating customers’ demand for the automotive sector, and the Internet of Things in general, were some of the main problems causing chaos in the industry. The paper studies the state-of-the-art and the solutions offered by the semiconductor industry and by the initiatives that Europe, the USA, and especially China, took to make companies and their countries take the most out of this situation.

Review on Formalization of Business Model Evaluation for Technological Companies with Focus on the Electronic Design Automation Industry

Abstract The paper aims to help the process of problem-solving and task formalization, from a business point of view, in the Electronic Design Automation (EDA) Industry, operating in dynamic environments with many influencing factors. High-Tech industries are under continuous pressure to innovate their products and not all companies can keep up with the latest trends. To formalize problems related to business model evaluation in the EDA industry, first, a review was done to look for mathematical and non-mathematical methods used in the business model evaluation field. The following were chosen as possible to apply and adapted for our problem definition, formulation, and solving: Set and Topos theory, Factor analysis, Structural equation modeling, Partial least square, Game theory, System dynamics, PESTEL analysis, and Scenario planning. In the last section, suggestions on how to apply these methods for EDA industry and problem formalization of an EDA company are proposed.

Data Analysis Environment to Study the Dynamics in Electronic Design Automation Industry

Abstract The Electronic Design Automation (EDA) industry is one of the most complex and dynamic industries. In the pressure of continuous technological turbulence, changing market demands, and industry convergence EDA companies find it difficult to adapt. This is one of the industries characterized by a large Merger and Acquisition activity. This paper presents results about EDA industry dynamics taken by a data analysis environment developed specifically to study the data for this industry and companies operating in this technological turbulent environment.

Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)

Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to determine the proper operation of the integrated circuits at the design phase, but is made very difficult by the sheer size of modern power grids, reaching quite a few million nodes in nanometer-scale integrated circuits. This paper presents two efficient and highly parallel preconditioning mechanisms for the analysis of large-scale power grids of near-2-D structure (with small via resistances) or 3-D structure (with large via resistances) by iterative solution methods. The proposed preconditioners approximate the matrices of practical power grids well enough to ensure fast convergence of the iterative method, while their application within the core of the method is based on a fast transform solver which makes use of a series of independent fast Fourier transforms. Apart from the near-optimal operation complexity, the main characteristics of a fast transform solver are the large degree of multilevel parallelism and low memory requirements, which enable harnessing the computational resources of massively parallel architectures like graphics processing units (GPUs). Experimental evaluation of the proposed methodology on a set of large-scale industrial benchmarks demonstrates nearly two orders of magnitude speedup and reduction in memory footprint over parallel implementations of state-of-the-art direct and iterative methods, when GPUs are utilized.

Automated Routing for VLSI: Kuh's Group Contributions

EDA (Electronic Design Automation) industry is now a multibillion dollar business and numerous commercial and university tools exist to automatically solve various sub-problems of the IC (integrated circuit) design process. Many of the underlying ideas of the algorithms implemented in those programs originated in Professor Ernest Kuh's research group at UC Berkeley. The objective of this paper is to trace Kuh's group contributions to EDA , to bring attention to this group's many accomplishments in physical design area and to show the effects that the ideas which originated in Kuh's group have had on researchers throughout the years. We limit our attention to routing problems only.

Cloud Computing for VLSI Floorplanning Considering Peak Temperature Reduction

Cloud computing has recently emerged as a promising computing paradigm, which offers unprecedented computing power and flexibility in the distributed computing environment. Despite the trend that electronic design automation industry has prepared to embrace the cloud concept, there is still no research publication on designing VLSI floorplanning algorithms for a cloud computing platform. This paper proposes the first such algorithm for thermal driven floorplanning. Since the existing floorplanning techniques are based on simulated annealing that are sequential algorithms and difficult to parallelize, a new thermal driven floorplanning algorithm is proposed, which can be easily parallelized in a cloud computing environment. This algorithm uses an advanced adjacency probability cross entropy optimization and a new integer linear programming-based resources provisioning to efficiently use the heterogeneous computation resources and handle the uncertainty of machine waiting time in a cloud. The experimental results on the standard GSRC benchmark circuits demonstrate that the proposed algorithm can significantly reduce the peak temperature (up to 24 °) compared with the simulated annealing technique. In the simulated cloud computing environment, it runs over 30% faster than the simulated annealing technique with moderate overhead in monetary expense due to the fact that the proposed algorithm is parallelization friendly. Further, our algorithm can effectively compute the scheduling solutions considering the uncertainty in waiting time.

Design and Implementation of an Ethernet MAC IP Core for Embedded Applications

<!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:RelyOnVML /> <o:AllowPNG /> </o:OfficeDocumentSettings> </xml><![endif]--> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications.<span style="mso-spacerun: yes;"> </span></span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt; mso-bidi-font-size: 10.0pt; color: black; mso-bidi-font-weight: bold; mso-no-proof: yes;"><span style="mso-spacerun: yes;"> </span>In this paper a</span><span style="font-size: 9.0pt;"> project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.</span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. </span></p> <!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables /> <w:SnapToGridInCell /> <w:WrapTextWithPunct /> <w:UseAsianBreakRules /> <w:UseFELayout /> </w:Compatibility> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style>
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And the winner is—Acquired. Entrepreneurship as a contest yielding radical innovations

New entrants to a market tend to be superior to incumbents in originating radical innovations. We provide a new explanation for this phenomenon, based on markets for technology. It applies in industries where successful entrepreneurial firms, or their technologies, are acquired by incumbents that then commercialize the innovation. To this end we analyze an innovation game between one incumbent and a large number of entrants. In the first stage, firms compete to develop innovations of high quality. They do so by choosing, at equal cost, the success probability of their R&D approach, where a lower probability accompanies higher value in case of success—that is, a more radical innovation. In the second stage, successful entrants bid to be acquired by the incumbent. We assume that entrants cannot survive on their own, so being acquired amounts to a prize in a contest. We identify an equilibrium in which the incumbent performs the least radical project. Entrants pick pairwise different projects; the bigger the number of entrants, the more radical the most radical project. Generally, entrants tend to choose more radical R&D approaches and generate the highest value innovation in case of success. We illustrate our theoretical findings by a qualitative empirical study of the Electronic Design Automation industry, and derive implications for research and management.

Design automation of ΔΣ switched capacitor modulators using spice and MATLAB

Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.

RFID based access control protection scheme for SRAM FPGA IP cores

Field-programmable gate-array (FPGA) based hardware IP cores have emerged as an integral part of modern SOC designs. IP trading plays central role in Electronic Design Automation (EDA) industry. While the potential of IP infringement is growing fast, the global awareness of IP protection remains low. In this work, we propose a Radio Frequency Identification (RFID) based protection scheme for Intellectual Property Protection (IPP) of Static Random Access Memory (SRAM) FPGA IP cores that overcome the limitations of existing IPP techniques. Here, three types of reconfigurable RFID tags is realised in order to support the incorporation of the proposed RFID based security scheme in all the reconfigurable FPGA devices of Xilinx family. Also a special tag bypass feature is employed to increase the suitability of proposed scheme as an IPP technique for reconfigurable IP cores. The proposed scheme supports safe exchange of reconfigurable FPGA IP cores between IP providers and system developers. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging and shows that the proposed security feature can be incorporated into the reconfigurable IP cores of any functionality without significant performance degradation of the reconfigurable IP cores.

Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse

SUMMARYThe current integrated circuit technologies are approaching their physical limits in terms of scaling and power consumption, in this context, the electronic design automation (EDA) industry is pushed towards solving ever more challenging problems in terms of performance, scalability and adaptability. Meeting these constraints needs innovation at both the algorithmic and the methodological level. Amongst academic EDA tools, Madeo toolkit has been targeting field‐programmable gate array (FPGA) design‐automation at the logic and the physical level since the late 1990s. As many other long‐living software, despite embedding valuable legacy, Madeo exhibits unwanted characteristics that penalize evolution and render the automation problems even more difficult. This study presents a methodological approach to physical‐design automation relying on model‐driven engineering, which is illustrated through the incremental redesign of the Madeo framework. A benefit of this approach is the emergence of a common vocabulary to describe the EDA domain in an FPGA scope. A second advantage is the isolation of the optimization algorithms from the structural domain models. However, the main asset is the possibility to re‐inject into the newly designed toolkit most of the legacy code. The redesigned framework is compared with and scored against initial code‐base, and demonstrates a regression‐free remodeling of the environment with net improvements in terms of size and complexity metrics. As a consequence, the evolution capability is back on stage, and the domain‐space exploration widens to the algorithmic axis. Copyright © 2013 John Wiley & Sons, Ltd.

(Invited) The Human Factor in Mixed-Signal Design and Its Consequences for Design and Automation

The semiconductor industry historically has made strong statements about analog circuits to diminish in applications. In parallel electronic design automation (EDA) industry has been committed to enable a high level of analog design automation. However, today analog circuit design reality does not look very different to the status 10 years ago – and analog design is still a common discipline in semiconductor manufacturing. This paper will analyze reason why analog design is still important and why analog design automation is not as successful as its digital counterpart. It is shown that analog circuit complexity strongly increases with the trend towards building systems on chip. Therefore solving today’s mixed signal design problems is becoming urgent. Overall here the situation is not very different from the digital verification crisis we have seen some years back in the past.

EDA meets biology! The bumpy road ahead [Perscetives

Before the 1970s, design automation was used more intensely in mechanical and civil engineering. In the 1970s, it became clear that the design of electrical and electronic circuits could be greatly aided by software tools. These tools enabled the creation of a novel electronic design automation (EDA) industry that claimed its space in the software industry. Today there is not a single IC company that does not use EDA tools. But because of this fact, EDA's overall market is saturated and enjoys modest growth. Much has been talked about extending EDA in the system space. To the rescue of a difficult path to double digit growth in EDA comes Synthetic Biology! Synthetic biology is about the synthesis of complex biological systems to obtain behaviors that do not exist in nature. A METHODOLOGY HAS come to the rescue within the past decade to reduce complexity, and to provide abstraction and design composability. The methodology is based on the availability of biological primitives: DNA-encoded 'Parts' are designed and then assembled to create modular 'Devices' that can be integrated into a host organism or assembled into a larger 'System.' This process resembles very much what we do today with integrated circuits. This methodology has enabled the development of design tools and a new discipline has emerged: Biology Design Automation (BDA). Workshops related to biodesign automation are appearing at traditional EDA venues (DAC), bioinformatics conferences (ISMB), and synthetic biology meetings (SB X.0). The way for EDA to extend to a new exciting field through the systematic construction of biological circuits maybe bumpy with detours, but eventually will enable the creation of a new industry by providing tools that make the design of living systems a true engineering discipline which is safe and effective.

Making Money from Exploiting Schumpeterian Opportunities: John Sanguinetti and the Electronic Design Automation Industry

IntroductionAn entrepreneur is a person who recognizes an opportunity and acts to capture economic rewards derived from exploiting it. There are two types of entrepreneurial opportunities, one that is linked to Joseph Schumpeter’s work (1942) and the other to Israel Kirzner’s work (1973).John Sanguinetti launched two companies that had significant effects on the electronic

Making Money from Exploiting Schumpeterian Opportunities: John Sanguinetti and the Electronic Design Automation Industry

IntroductionAn entrepreneur is a person who recognizes an opportunity and acts to capture economic rewards derived from exploiting it. There are two types of entrepreneurial opportunities, one that is linked to Joseph Schumpeter’s work (1942) and the other to Israel Kirzner’s work (1973).John Sanguinetti launched two companies that had significant effects on the electronic

Fast and accurate statistical characterization of standard cell libraries

With devices entering the nanometer scale process-induced variations, intrinsic variations and reliability issues impose new challenges for the electronic design automation industry. Design automation tools must keep the pace of technology and keep predicting accurately and efficiently the high-level design metrics such as delay and power. Although it is the most time consuming, Monte Carlo is still the simplest and most employed technique for simulating the impact of process variability at circuit level. This work addresses the problem of efficient alternatives for Monte Carlo for modeling circuit characteristics under statistical variability. This work employs the error propagation technique and Response Surface Methodology for substituting Monte Carlo simulations for library characterization. The techniques are validated and compared using a production level cell library using a state-of-the-art 32 nm technology node and statistical device compact model. They require electrical simulation effort linear to the number of devices, thus from one to two orders of magnitude speed-up is obtained compared to Monte Carlo analysis with the error on standard deviation and mean being smaller than 2% for the Response Surface Methodology, as compared to errors of 7% when using linear sensitivity analysis.

Acquisitions as a means of innovation sourcing by incumbents and growth of technology-oriented ventures

The permanent need for innovation activities in high tech industries challenges large firms. Small firms, on the other hand, frequently face decisions as concerns their growth which may, e.g., in the case of lacking complementary assets, lead them to sell-off to larger incumbents. This paper investigates how this leads to a division of innovation activities between large and small firms in the electronic design automation (EDA) industry. Based on qualitative interviews and a structured survey the paper analyses empirically the reasons for acquisitions and shows that these mainly concern small firms that pursue (especially organisationally) radical innovation and that they enable radical growth of small firms.

Analog Circuit Design in Nanoscale CMOS Technologies

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vsb</i> > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vsb</i> > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design

System-level design (SLD) is considered by many as the next frontier in electronic design automation (EDA). SLD means many things to different people since there is no wide agreement on a definition of the term. Academia, designers, and EDA experts have taken different avenues to attack the problem, for the most part springing from the basis of traditional EDA and trying to raise the level of abstraction at which integrated circuit designs are captured, analyzed, and synthesized from. However, my opinion is that this is just the tip of the iceberg of a much bigger problem that is common to all system industry. In particular, I believe that notwithstanding the obvious differences in the vertical industrial segments (for example, consumer, automotive, computing, and communication), there is a common underlying basis that can be explored. This basis may yield a novel EDA industry and even a novel engineering field that could bring substantial productivity gains not only to the semiconductor industry but to all system industries including industrial and automotive, communication and computing, avionics and building automation, space and agriculture, and health and security, in short, a real technical renaissance. In this paper, I present the challenges faced by industry in system level design. Then, I propose a design methodology, platform-based design (PBD), that has the potential of addressing these challenges in a unified way. Further, I place methodology and tools available today in the PBD framework and present a tool environment, Metropolis, that supports PBD and that can be used to integrate available tools and methods together with two examples of its application to separate industrial domains

Local watermarks: Methodology and application to behavioral synthesis

Recently, the electronic design automation industry has adopted the intellectual property (IP) business model as a dominant system-on-chip development platform. Since copyright fraud has been recognized as the most devastating obstruction to this model, a number of techniques for IP protection have been introduced. Most of them rely on a selection of a global solution to a design optimization problem according to a unique user-specific digital signature. Although such techniques provide strong proof of authorship, they fail to provide an effective procedure for watermark detection when a protected core design is augmented into a larger design. To address this fundamental issue, we introduce local watermarks, an IP protection technique which facilitates watermark detection in many realistic design and adversarial scenarios, while satisfying the demand for low overhead and design transparency. We demonstrate the efficiency of the new IP protection paradigm by applying its principles to a set of behavioral synthesis tasks such as operation scheduling and template matching.