Electron Schottky Barrier Height Research Articles

High-performance Schottky-barrier field-effect transistors based on two-dimensional GaN with Ag or Au contacts

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

Fermi-level depinning in Mo/Si junctions by insertion of amorphous Si-rich Mo silicide film formed via gas-phase reactions of MoF6 with SiH4

We demonstrate the reduction of the electron Schottky barrier height (SBH) to 0.48 eV at Mo/n-type Si junctions through the insertion of a semimetal Si-rich Mo silicide (MoSi n , n = 7.9) film. Raman scattering measurements elucidated the persistence of the same amorphous structure within the MoSi n film even when subjected to temperatures as high as 900 °C. This excellent thermal stability yielded a notable result: preservation of the SBH modulation effect even following annealing at 700 °C. Moreover, we investigated the capacitance−voltage characteristics of MOS capacitors, revealing that MoSi n film has a remarkably low effective work function, measuring 4.1 eV when deposited onto SiO2. The deposition of MoSi n film was accomplished with an excellent coverage by using MoF6 and SiH4 gases. Thus, MoSi n film is a promising contact material in advanced CMOS transistors.

Strain-tuned full spin polarization and ndoping of phosphorene via the phosphorene/Co[formula omitted]Sn[formula omitted]S[formula omitted] heterojunction

Phosphorene’s desired bandgap, high carrier mobility and weak spin–orbit coupling qualify it as an exceptional semiconductor spin channel material. These traits underscore the importance of examining phosphorene’s electronic structure and that of half-metal heterojunctions (HJs) in innovating spintronic device design. This paper methodically investigates the electronic structure and Schottky barrier (SB) of a van der Waals HJ, comprising phosphorene and the half-metal Co3Sn3S2, subjected to biaxial mechanical strain via a first-principles method. The investigation unveils that phosphorene, as an n-type semiconductor, possesses substantial spin polarization. Remarkably, phosphorene undergoes three states – metallic, half-metallic, and semiconducting – subject to varying strain ratios (E). Furthermore, we discern that phosphorene’s spin polarization, peaking at 100% for −2%<E<1%, is tunable with strain. The SB heights (SBHs) also exhibit a consistent escalation with strain: for −5%≤E<1%, the electron SBH is 0 eV, which increments from 0.017 eV to 0.021 eV for 1%≤E≤3%. Intriguingly, the spin-down band alignment of the HJ transitions from type-II to type-I at E= 3%. Our Bader charge analysis validates that the n-doping of phosphorene is primarily due to electron acceptance from Co3Sn3S2. The orbital hybridizations between phosphorene and Co3Sn3S2 leads to complete spin polarization of phosphorene. Collectively, these observations confirm phosphorene’s capability to attain n-type doping with 100% spin polarization. Moreover, our findings suggest the possibility to modulate both the bandgap of phosphorene and the SBHs of the HJ with strain. This highlights the potential of the phosphorene/Co3Sn3S2 HJ in advancing the field of low-dimensional, flexible spintronics.

Isotropic Contact Properties in Monolayer GeAs Field-Effect Transistors

Owing to the tunable bandgap and high thermodynamic stability, anisotropic monolayer (ML) GeAs have arisen as an attractive candidate for electronic and optoelectronic applications. The contact properties of ML GeAs with 2D metal (graphene, Ti2CF2, V2CF2, and Ti3C2O2) and Cu electrodes are explored along two principal axes in field-effect transistors (FET) by employing ab initio electronic structure calculations and quantum transport simulations. Weak van der Waals interactions are found between ML GeAs and the 2D metal electrodes with the band structure of ML GeAs kept the same, while there is a strong interaction between ML GeAs and the Cu metal electrode, resulting in the obvious hybridization of the band structure. Isotropic contact properties are seen along the two principal directions. P-type lateral Schottky contacts are established in ML GeAs FETs with Ti3C2O2, graphene, and Ti2CF2 metals, with a hole Schottky barrier height (SBH) of 0.12 (0.20), 0.15 (0.11), and 0.29 (0.21) eV along the armchair (zigzag) direction, respectively, and an n-type lateral Schottky contact is established with the Cu electrode with an electron SBH of 0.64 (0.57) eV. Surprisingly, ML GeAs forms ideal p-type Ohmic contacts with the V2CF2 electrode. The results provide a theoretical foundation for comprehending the interactions between ML GeAs and metals, as well as for designing high-performance ML GeAs FETs.

Quaternary, layered, 2D chalcogenide, Mo1−x W x SSe: thickness dependent transport properties

Highly oriented, single crystalline, quaternary alloy chalcogenide crystal, Mo x W1−x S2y Se2(1−y), is synthesized using a high temperature chemical vapor transport technique and its transport properties studied over a wide temperature range. Field effect transistors (FET) with bottom gated configuration are fabricated using Mo0.5W0.5SSe flakes of different thicknesses, from a single layer to bulk. The FET characteristics are thickness tunable, with thin flakes (1–4 layers) exhibiting n-type transport behaviour while ambipolar transfer characteristics are observed for thicker flakes (>90 layers). Ambipolar behavior with the dominance of n-type over p-type transport is noted for devices fabricated with layers between 9 and 90. The devices with flake thickness ∼9 layers exhibit a maximum electron mobility 63 ± 4 cm2 V−1s−1 and an I ON/I OFF ratio >108. A maximum hole mobility 10.3 ± 0.4 cm2 V−1s−1 is observed for the devices with flake thickness ∼94 layers with I ON/I OFF ratio >102–103 observed for the hole conduction. A maximum I ON/I OFF for hole conduction, 104 is obtained for the devices fabricated with flakes of thickness ∼7–19 layers. The electron Schottky barrier height values are determined to be ∼23.3 meV and ∼74 meV for 2 layer and 94 layers flakes respectively, as measured using low temperature measurements. This indicates that an increase in hole current with thickness is likely to be due to lowering of the band gap as a function of thickness. Furthermore, the contact resistance (R ct) is evaluated using transmission line model (TLM) and is found to be 14 kohm.μm. These results suggest that quaternary alloys of Mo0.5W0.5SSe are potential candidates for various electronic/optoelectronic devices where properties and performance can be tuned within a single composition.

Low specific contact resistance between InAs/Ni–InAs evaluated by multi-sidewall TLM

The specific contact resistance ρint of the InAs/Ni–InAs interface was evaluated by the multi-sidewall transmission line method (MSTLM), where Ni–InAs was formed by alloying Ni and InAs-on-insulator substrates. The revised test structure for MSTLM has been proposed, which can be easily fabricated. By evaluating each component of the parasitic resistance separately, the specific contact resistance of the InAs/Ni–InAs was accurately extracted. As a result, the record low ρint of (4.3 ± 2.5) × 10−9 Ω cm2 among metal/III-V contacts was obtained for the 30-nm-thick InAs/Ni–InAs interface with the average electron concentration of 9.1 × 1018 cm−3 for InAs, which is close to the Landauer limit. The comparison of the experimental and theoretical ρint indicates that there is no potential barrier at the InAs/Ni–InAs interface, which is attributable to the negative Schottky barrier height for electrons of InAs.

Field cycling behavior and breakdown mechanism of ferroelectric Al0.78Sc0.22N films

The effects of field cycling of Al0.78Sc0.22N capacitors on ferroelectric properties are investigated. In the first hundreds of switching cycles, the reduction in the switching voltage was observed, possibly due to the formation of nitrogen-vacancy to facilitate the atom displacements. With further switching cycles, fatigue effect was observed, especially for domains with low switching voltage. The leakage current analysis indicates continuous downward band bending with the number of switching cycles, effectively reducing the Schottky barrier height for electrons. The breakdown of Al0.78Sc0.22N films is triggered by the Joule heat due to excessive leakage current. The mechanism is in contrast to conventional ferroelectric materials, where the breakdown is triggered by Joule heat at the local conductive filaments.

Oxygen vacancy concentration as a function of cycling and polarization state in TiN/Hf0.5Zr0.5O2/TiN ferroelectric capacitors studied by x-ray photoemission electron microscopy

We have studied the field cycling behavior of microscopic TiN/Hf0.5Zr0.5O2/TiN ferroelectric capacitors using synchrotron-based soft x-ray photoemission electron microscopy. The oxygen vacancy (VO) concentration near the top TiN/Hf0.5Zr0.5O2 interface is estimated from the reduction of Hf4+ to Hf3+ as measured in the Hf 4f core level spectra. The VO concentration increases with field cycling and redistributes under the effect of the internal field due to the polarization. Upward pointing polarization slightly depletes the concentration near the top interface, whereas downward polarization causes VO drift toward the top interface. The VO redistribution after wake-up is consistent with shifts in the I–V switching peak. The Schottky barrier height for electrons decreases systematically with cycling in polarization states, reflecting the overall increase in VO.

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band into the channel valence band during the OFF-state. Impact of varying WF at channel–drain junction on the device characteristics is studied. It is observed that SBH \(\leqslant 0\) eV is required to mitigate L-BTBT compared to the conventionally doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and is termed as the lateral SB tunneling (L-SBT). In contrast with JL NW FET, the process variation immunity (varying channel doping, \({N}_{\mathrm{Ch}}\) and NW diameter, \({d}_{\mathrm{NW}}\)) and the ON-state current of the proposed device are not compromised at the expense of lower OFF-state L-SBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ± 20% change in \({N}_{\mathrm{Ch}}\), \(\Delta {I}_{\mathrm{OFF}}\)/\({I}_{\mathrm{OFF}}\) of 7% compared to 97% in NW JL FET is observed.

Ohmic contacts of monolayer Tl2O field-effect transistors

Monolayer (ML) Tl2O, as a newly discovered metal-shrouded two-dimensional semiconductor with an appropriate bandgap and high carrier mobility, is a promising candidate as the channel materials for the next-generation field-effect transistors (FETs). Using ab initio electronic structure calculation and quantum transport simulation, the contact properties of ML Tl2O–metal interfaces based on FET are comprehensively investigated with Au, Sc, Tl, Ni, graphene, Ti2C, Ti2CF2, and Ti2C(OH)2 electrodes. ML Tl2O undergoes metallization with Au, Sc, Tl, Ni, and Ti2C, while it forms van der Waals-type contact with graphene, Ti2CF2, and Ti2C(OH)2. An n-type lateral Schottky contact is formed with Ni, Au, Sc, and Ti2C electrodes with the electron Schottky barrier height (SBH) of 0.25, 0.27, 0.27, and 0.36 eV, respectively, while a p-type lateral Schottky contact is formed with graphene electrode with the hole SBH of 0.10 eV. Surprisingly, a desired n-type Ohmic contact arises with Tl and Ti2C(OH)2 electrodes and a desired p-type Ohmic contact arises with Ti2CF2 electrode. The study not only provides a deep understanding of the interfacial properties of the ML Tl2O FETs but also reveals a versatile approach to realize both n- and p-type Ohmic contact for the ML Tl2O FETs.

Amorphous Si-rich tungsten silicide with a low work function near the conduction band edge of Si

The capacitance–voltage characteristics of MOS capacitors and ab initio theoretical calculations revealed that an amorphous film composed of WSin clusters (n = 6−12) had a low effective work function of 4.0 eV on SiO2 with excellent thermal stability up to 600 °C. In Si Schottky diodes with WSin insertion, the electron Schottky barrier height (SBH) was 0.58 eV for n = 6 and reduced to 0.45 eV when n = 12. The n-dependency of SBH was attributed to the surface passivation of WSin becoming more effective as n increased, with annealing leading to a lower value of 0.32 eV.

Physical chemistry of the TiN/Hf0.5Zr0.5O2 interface

Ferroelectric hafnia-based thin films are promising candidates for emerging high-density embedded nonvolatile memory technologies, thanks to their compatibility with silicon technology and the possibility of 3D integration. The electrode–ferroelectric interface and the crystallization annealing temperature may play an important role in such memory cells. The top interface in a TiN/Hf0.5Zr0.5O2/TiN metal–ferroelectric–metal stack annealed at different temperatures was investigated with X-ray photoelectron spectroscopy. The uniformity and continuity of the 2 nm TiN top electrode was verified by photoemission electron microscopy and conductive atomic force microscopy. Partial oxidation of the electrode at the interface is identified. Hf is reduced near the top interface due to oxygen scavenging by the top electrode. The oxygen vacancy (VO) profile showed a maximum at the top interface (0.71%) and a sharp decrease into the film, giving rise to an internal field. Annealing at higher temperatures did not affect the VO concentration at the top interface but causes the generation of additional VO in the film, leading to a decrease of the Schottky Barrier Height for electrons. The interface chemistry and n-type film doping are believed to be at the origin of several phenomena, including wake-up, imprint, and fatigue. Our results give insights into the physical chemistry of the top interface with the accumulation of defective charges acting as electronic traps, causing a local imprint effect. This may explain the wake-up behavior as well and also can be a possible reason of the weaker endurance observed in these systems when increasing the annealing temperature.

High-Performance Schottky-Barrier Field-Effect Transistors Based on Monolayer SiC Contacting Different Metals

Schottky-barrier field-effect transistors (SBFETs) based on monolayer SiC contacting four metals (Ag, Au, Al, and Pd) have been proposed using density functional theory and ab initio simulations. The n-type Schottky contacts could be formed between monolayer SiC and Ag, Au electrodes with electron Schottky barrier heights (SBHs) of 0.7 and 1.1 eV, respectively, whereas the p-type Schottky contacts were formed between monolayer SiC and Al, Pd electrodes with hole SBHs of 1.0 and 0.1 eV, respectively. When the gate length was equal to 5.1 nm, SiC-SBFETs with four metals could all overcome the short-channel effect due to the wide bandgap of SiC. In addition, the SiC-SBFET with Pd electrode provided the best performance and could satisfy the performance requirement of high-performance transistor with gate length of 5.1 nm outlined by the International Technology Roadmap for Semiconductors (ITRS). Our study gives an insight into the monolayer SiC–metal interfaces and, thus could be developed into a viable 5-nm “More than Moore” device in the future.

Engineering the interface chemistry for scandium electron contacts in WSe2 transistors and diodes

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS2, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe2 transistors with impressive subthreshold slope (109 mV dec−1) and ION/IOFF (106) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe2 in situ before metallization, which minimizes subsequent reactions between Sc and WSe2. Post metallization anneals in reducing environments (UHV, forming gas) degrade the ION/IOFF by ~103 and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe2, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe2 layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe2 Fermi level around individual Sc atoms in the WSe2 lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe2 transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe2.

P‐198: Late‐News Poster: Off‐Current Reduction in p‐Type SnO Thin‐Film Transistors through Fermi‐Level Unpinning

High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10‐8 A to 2.4 × 10‐9 A and the enhancement of the ION/OFF from 2.7 × 102 to 2.8 × 103 compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs.

Interstitial copper‐doped edge contact for n‐type carrier transport in black phosphorus

AbstractBlack phosphorus (BP) has been shown as a promising two‐dimensional (2D) material for electronic devices owing to its high carrier mobility. To realize complementary electronic circuits with 2D materials, it is important to fabricate both n‐type and p‐type transistors with the same channel material. By engineering the contact region with copper (Cu)‐doped BP, here we demonstrate an n‐type carrier transport in BP field‐effect transistors (FETs), which usually exhibit strongly p‐type characteristics. Cu metal atoms are found to severely penetrate into the BP flakes, which forms interstitial Cu (Cuint)‐doped edge contact and facilitates the electron transport in BP. Our BP FETs in back‐gated configuration exhibit n‐type dominant characteristics with a high electron mobility of ~ 138 cm2 V−1 s−1 at room temperature. The Schottky barrier height for electrons is relatively low because of the edge contact between Cuint‐doped BP and pristine BP channel. The contact doping of BP by highly mobile Cu atoms gives rise to n‐type transport property of BP FETs. Furthermore, we demonstrate a p‐n junction on the same BP flake with asymmetric contact. This strategy on contact engineering can be further extended to other 2D materials.

(Invited) Cluster-Preforming-Deposited Si-Rich W Silicide: A New Contact Material for Advanced CMOS

With recent shrinkage of Si CMOS, the contact resistance at source/drain (S/D) and the external series resistance are becoming determining factors of device performance. Low Schottky barrier height (SBH) at the metal/semiconductor interface is required to reduce the specific contact resistivity. It is well known, however, that for most metallic species, silicide/Si junctions always show a high electron SBH to n-Si owing to the Fermi-level pinning in the range between the mid gap and the valence band edge. This fact imposes a fundamental difficulty for obtaining low contact resistance and high performance in CMOS. Many researchers have already addressed this issue; yet, an unconventional contact material is strongly required. In this work, we demonstrate a novel contact material with low SBH for both n- and p-FET together with excellent diffusion barrier properties: the WSi n (n = 12) composed of W-atom-encapsulated Si n cage clusters.[1] The WSi n film was prepared by the newly developed Cluster-Preforming Deposition (CPD) method.[2] In a hot-wall thermal deposition system, hydrogenated W-atom-encapsulated WSi n H x clusters with well-controlled n values (n ≤ ~12) are preformed by reaction of WF6 and SiH4 in the gas phase. The WSi n H x clusters are then deposited onto a substrate, where they are thermally dehydrogenated and coalesce to the WSi n film with less hydrogen content. The residual fluorine concentration in the film was less than ~0.1 at. % because of the sufficient reduction reaction of WF6 with SiH4 in the gas phase. The formed films have an amorphous structure similar to the hydrogenated amorphous Si, but they are extremely stable against annealing up to 1100 °C.[3] The power formation is entirely suppressed under the CPD condition of very high flow ratio of SiH4/ WF6. We also confirmed that the CPD WSi n exhibits an excellent step coverage over a high-aspect-ratio hole array with 40-nm diameter and 2-μm depth. We evaluated the insertion effect of WSi n film of 5-10 nm thickness into Schottky diodes with high resistivity Si substrates: W/WSi n /n-Si (~2 Ω·cm) and W/WSi n /Ge/p-Si (~5 Ω·cm). The electron SBH in the inserted diodes decreases with n, and in particular, is most reduced to 0.32 eV when n is 12. This indicates that the WSi n film has a Fermi level close to the Si conduction band edge and sufficiently passivates the interfacial states at the Si surface because WSi n is composed of almost Si. This SBH reduction effect is kept even after annealing up to at 700 °C. On the other hand, for the W/WSi n /Ge/p-Si junction, the hole SBH once increases by the insertion but is reduced with annealing temperature, approaching the charge neutrality level close to the valence band edge of Ge, e.g. 0.51 eV with n = 12 after annealing at 600 °C. This property enables the WSi12 film to reduce both the electron and hole SBHs simultaneously in CMOS. Furthermore, the WSi n is a narrow gap semiconductor with a low offset to the band edge of Si or Ge. This band alignment leads to the negligible insertion resistance. To reduce the parasitic series resistance at S/D, it is effective to adopt a thinner barrier film for a low resistance electrode such as Cu. Thus, the barrier properties of the WSi n film against Cu diffusion were investigated using the two test structures: MOS capacitors with a 20-nm thermal oxide and p+-n diodes (junction depth of 100 nm) with and without the WSi n insertion (n = 12, thickness = 5 nm). The WSi n film exhibited excellent diffusion barrier properties for Cu contact; from the TDDB lifetime of the Cu MOS capacitors, the diffusion barrier height was estimated to be 1.33 eV under 5 MV/cm stress and the Cu on Si diodes were stable against annealing up to 600 °C. In conclusion, the insertion of the CPD WSi n (n = 12) film is demonstrated to reduce the electron and hole SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly preventing the Cu diffusion with a TDDB barrier height of 1.33 eV under 5 MV/ cm stress. Consequently, this film is a promising contact material for S/D in CMOS. [1] IEDM, 22.5, (2017). [2] J. Chem. Phys., 144, 084703 (2016). [3] J. Appl. Phys., 121, 225308, (2017).

Tunable Ohmic, p-Type Quasi-Ohmic, and n-Type Schottky Contacts of Monolayer SnSe with Metals

Monolayer (ML) SnSe, a p-type IV–VI semiconductor, has drawn tremendous attention because of its chemical stability, high electrostatic gating efficiency, and carrier mobility, and it has been synthesized in different ways. We have comprehensively investigated the properties of the interfaces between ML SnSe and some regular metals by using first-principles calculations. Metallization of ML SnSe appears in ML SnSe–Ag, −Al, −Au, −Cu, and −Cr systems. Lateral n-type Schottky contacts with electron Schottky barrier heights of 0.42 and 0.32 eV are formed, respectively, when ML SnSe contacts with metals Ag and Al. Also, a lateral p-type quasi-ohmic contact with a hole Schottky barrier height of 0.02 eV is formed when ML SnSe contacts with metal Au. Surprisingly, ohmic contacts are formed when ML SnSe contacts with metals Cr and Cu. Our research not only has a deep understanding of the characteristics of the interfaces between ML SnSe and the metals but also offers a reference in the electrode selection for ML SnSe devices.

Schottky Contact in Monolayer WS2 Field‐Effect Transistors

AbstractMonolayer (ML) WS2 is a promising material to be the channel of nanoscale field‐effect transistors (FETs). In ML WS2 FETs, the interfacial properties between ML WS2 and electrodes significantly affect the device performance, due to the possible existence of Schottky barriers at the interface. In this paper, the electronic and transport properties of both the lateral and the vertical interfaces between ML WS2 and six common metals is calculated (Sc, Ti, Ag, Cu, Au, and Pt) by the density functional theory and the quantum transport simulation. n‐type Schottky contact exists with the lateral electron Schottky barrier height (SBH) of 0.28, 0.36, 0.25, 0.46, 1.00 eV for Sc, Ti, Ag, Cu, and Au electrode, respectively, while p‐type Schottky contact exists with the lateral hole SBH of 0.98 eV for Pt electrode. The average pinning factor at the lateral interface obtained from linear fitting to the SBHs and the Schottky–Bardin model is 0.32 and 0.28, respectively, suggestive of a strong Fermi level pinning originating from the metal induced gap states. The work reveals the properties of the lateral interfaces between ML WS2 channels and electrodes theoretically for the first time, providing an instruction to design ML WS2 devices.

Barrier formation at BaTiO3 interfaces with Ni and NiO

Barium Titanate and Ni-based multilayer ceramic capacitors have wide commercial applicability, and interfaces are critical to the overall device behavior as they can help control unwanted leakage currents. Here we make use of photoemission methods to investigate the electrostatic barriers formed at BaTiO3/Ni(O) interfaces to understand the implications for electron injection. We find the interface Fermi level in BaTiO3 to evolve smoothly during Ni deposition with a Schottky barrier height for electrons of 0.68 eV, whereas with NiO the Fermi level evolves rapidly with an electron injection barrier of 1.49 eV. In-situ poling shows the Schottky barrier at the BaTiO3/Ni interface is not significantly altered by ferroelectric polarization, consistent with the good screening of the Ni electrode. This study presents a direct quantitative measurement of the interface barrier heights and highlights the significance of the oxidation state of the electrode.