Electron Beam Testing Research Articles

Status of the Brookhaven National Laboratory high current electron beam ion source test stand

As part of a new, compact heavy ion injector for the AGS/RHIC complex at Brookhaven National Laboratory we are developing an electron beam ion source (EBIS) that would satisfy present and future requirements. Such a source should be capable of producing intensities of, e.g., Au35+ ions of about 3×109 particles/pulse or U45+ of about 2×109 particles/pulse. To achieve this, the required e-beam intensity is 10 A, at a pulse length of 100 ms. An EBIS test stand has been constructed, designed for the full electron beam power and having close to 1/2 of the trap length of an EBIS for RHIC. Initial electron beam tests have resulted in a 50 μs, 13 A electron beam. Ion production and extraction has been shown with a 3.1 A, 50 ms electron beam, achieving an ion yield of 19 nC/pulse (neutralization degree of 61%); fast extraction trials have yielded extracted ion pulses of 1 mA peak current and 18 μs at FWHM. Details of the test stand construction, results of the electron beam studies, and properties of the extracted ion pulse are presented.

Internal charging: a preliminary environmental specification for satellites

Internal charging has been indicated as the cause of many satellite anomalies. In some cases, it has been argued that internal charging has caused satellite system failures. It may be possible to predict the occurrence of an internal charging threat in the future but that does not remove the necessity to know what the environmental threat may be. The existence, for many years now, of energetic electron and internal charging measurements in the inner magnetosphere provides the ability to identify the threat levels and generate internal charging specifications. The specifications must embody the worst-case environments that can be expected from magnetic storms and extreme solar/interplanetary conditions. Internal-charging environment specifications are needed by satellite manufacturers for setting design requirements for their systems. The specifications are also required for defining the worst-case energetic electron flux levels and total fluence levels from events. These are used for electron beam testing to verify that critical systems are immune to internal charging, for performing tests on subsystems, and for use in anomaly investigation programs. Data from the GOES, LANL, and CRRES satellites were used to develop preliminary internal-charging environment specifications for some commonly used orbits such as geosynchronous and Molniya or high earth orbits (HEO), and they are discussed. A specification is also given for a highly elliptical equatorial orbit that is used for lunar-transfer orbital maneuvers. The preliminary environments were used to estimate the shielding required to reduce worst-case electron fluxes to safe levels for these orbits.

Fault and diagnosis on a successive approximation ADC

In successive approximation A/D converters, the origin of failure is located through the bit error which is computed from the histogram, if it fulfil some conditions. In this paper, we present the real case of a failing A/D converter whose bit error is not computable. Consequently, the failure localization is performed using an alternative methodology including external electrical characterization and electron beam testing (EBT).

Defect localization using voltage contrast IDDQ testing

IDDQ testing detects a majority of faults occurring in logic,ICs. Nethertheless, it has not eliminated the complex task of fault isolation at the silicon level of ICs. Liquid Crystak or Emission Microscopy can deal with this challenge. Unfortunately these two techniques lack sensitivity for some defects when the abnormal current consumption (IDDQ) remains weak. On the other hand we can use very powerful tools like the electron beam tester to deeply analyze faulty devices by internal contactless testing. In some laboratories, people have underlined the interest of merging the two techniques (IDDQ testing and Voltage Contrast) to get fast and accurate defect localization. In this paper, we will move on to the next step of identifying practical key issues necessary for obtaining results on current VLSI.

Electron Beam Testing of FPGA Circuits

Abstract The growing use of FPGA circuits has made it necessary to perform accurate debug and internal testing of these circuits. To meet this challenge, we have developed an innovative method which makes it possible to use existing Electron Beam Testers to investigate the internal functionality of programmable circuits. This approach is based on the generation of a circuit layout linked to the electrical schematic for contactless measurement on the circuit.

Performance of tungsten coatings as plasma facing components used in ASDEX Upgrade

Tungsten coated graphite tiles were mounted in the divertor of the ASDEX Upgrade tokamak and exposed to approximately 800 plasma discharges with varying average heat fluxes of up to 6 MW/m 2. After the experimental campaign, cracks were detected on almost all tiles in accordance with results of electron beam tests. The W-coated tiles in the inner divertor were found to be covered by deposited layers of low-Z material with thicknesses in the μm range and only a few percent tungsten remaining on the surface. In contrast the outer divertor is dominated by erosion. Here, the tungsten concentration at the surface was found to be close to the initial level. The global W-migration pattern was determined by analyzing the deposition of tungsten on a complete poloidal set of plasma facing wall components. Both divertor regions display broad deposition peaks with deposited layers at least one order of magnitude thicker than the main chamber values.

Fabrication and high heat flux testing of plasma sprayed beryllium ITER first wall mock-ups

Plasma-sprayed beryllium ITER first wall mock-ups have survived 3000 thermal fatigue cycles at 1 MW/m 2 without damage during testing at the Plasma Materials Test Facility at Sandia National Laboratory in New Mexico. This heat flux level is twice the expected design heat flux for ITER first wall modules. Plasma sprayed beryllium mock-ups were vacuum plasma sprayed at the Los Alamos National Laboratory's Beryllium Atomization and Thermal Spray Facility. Results will be reported on the fabrication, high heat flux testing and post-mortem analysis of two beryllium plasma sprayed mock-ups (1) beryllium plasma sprayed directly on a CuNiBe heat sink and (2) beryllium plasma sprayed on a compliant layer of aluminum which was explosion-bonded to a CuCrZr copper heat sink. The high heat flux tests utilized the 30 kW Electron Beam Test System at a Sandia National Laboratory.

Thermal fatigue testing of an ITER primary wall small scale mock up

A first primary wall small scale mock up with beryllium as the armor material was manufactured by hot isostatic pressing (HIPing) by CEA and tested at the electron beam test facility JUDITH. The mock up consisted of a 9.4 mm thick beryllium armor joint onto a 20 mm thick dispersion strengthened copper (DS-Cu) alloy plate. Type 316L Stainless Steel tubes, 10/12 mm in diameter were embedded in the DS-Cu, which was subsequently joined onto a 30 mm thick 316LN stainless steel plate. The mock up was tested under a surface heat flux of 2.5 MW m −2 for 100 preparatory cycles and 900 cycles of 30 s heating and 30 s cooling time. At the end of the 1000 cycles, the surface and the Be/DS-Cu joint of the mock up did not show any damage due to the fatigue test.

Mechanical behavior on residual stress in a tungsten-copper duplex structure after cyclic heat loads for a divertor application

Cyclic thermal tests have been carried out on the tungsten-copper duplex structures using an electron-beam test facility, with a particular emphasis on the redistribution of the residual stress after the cyclic heat loads of 14 MW/m 2–2 s. The residual stresses on the tungsten surfaces were measured by the strain gauge method and compared with those by thermoelasto–plastic analysis. Good agreement was approximately obtained for both their stress magnitude and distribution. Both radial and hoop stress components σ R and σ θ on the tungsten top surface slightly increased after first heat cycle and then decreased with the increase of the number of heat load cycles. Axial stress component σ z on the tungsten side surface also behaved in the same manner as stresses on the top surface, while hoop stress component increased with the increase of the number of heat cycles. Relaxation of residual stress was induced with the elastic-plastic deformation of copper heat sink by cyclic heat loads.

Electrical characterization and modification of a microelectroMechanical system (MEMS) for extended mechanical reliability and fatigue testing

The feasibility of microsystems has been achieved in the early 90's and is now followed by a growing industrialization period. Nevertheless, diversity of fields combined and materials heterogeneity generate new failure mechanisms different from traditional microelectronics. Now, if we take into account the lessons from the past in microelectronics, we note that failure analysis played a major role not only in development time reduction but also in qualification and reliability evaluation. That is why we decided to elaborate a specific failure analysis methodology for microsystems using existing instrumentation from microelectronics in order to prepare for present and future expert appraisement requirements in the micro-technologies field. For this, we chose to perform accelerated aging tests of a commercial micro-accelerometer. This paper demonstrates how we realized the reverse engineering of this MicroElectroMechanical System (MEMS) using an Electron Beam Tester (Integrated Diagnostic System : IDS-5000) and how we modified its functions with a Focused Ion Beam (FIB-P2X) in order to control its full mechanical capabilities with electrical stimulation.

Circuit internal logic analysis with electric force microscope- (EFM-) testing

In this paper the well known electron beam testing techniques stroboscopic voltage contrast and logic state mapping are realized for an EFM-testing system. These testing techniques allow an advanced logic analysis of digital circuits. They are based on a linear interaction, a pulse sampled measurement method and a scanned EFM-tip. First measurement results are shown on an integrated bus structure of 2 μm feature size with applied clock signals at few megahertz frequencies pointing out the ability for simultaneous temporal and spatial frequency measurements with EFM-testing, as well. Further improvements promise the applicability of these proven testing techniques in integrated circuits with structure dimensions beyond the limits of electron beam testers.

Nuclear microprobe analysis and imaging: Current state of the art performances

The current state-of-the-art performances claimed for nuclear microbeam spatial resolutions are: (a) 400 nm spot sizes for high current (100 pA) proton beams, (b) 400 nm for high current alpha particle beams, (c) 100 nm for low proton current (<0.1 pA) applications such as Scanning Transmission Ion Microscopy (STIM) and Ion Beam Induced Charge (IBIC) and (d) 50 nm for low current alpha particles. These claims, however, have been undermined not only by the lack of a common and generally accepted resolution standard, but also by the lack of a consistent approach between groups regarding a recognised method of beam spot measurement. The lack of a definitive method for assessing spatial resolution is hindering the future development of nuclear microprobes to higher spatial resolutions. We require the manufacture of resolution standards specifically tailored for nuclear microprobe spot size measurements, for both high and low current operations. Until such resolution standards are available, one commercially available standard which has high potential for high current proton beam resolution tests is the Ebeam test chip manufactured for the characterisation of electron beam testers. This chip has patterns as small as 0.5 μm in size produced in 0.5 μm thick aluminium by direct electron beam writing. Using both analytical Particle Induced X-ray Emission (PIXE) imaging and PIXE line scans, the nuclear microscope facility at the National University of Singapore has demonstrated spatial resolutions of less than 400 nm for a 100 pA beam of 2 MeV protons. Low current resolution standards have more stringent requirements. One potential standard tested in Singapore is a prototype self-supporting X-ray mask used in X-ray lithography. This test standard, however, is not commercially available at the moment, is fragile and therefore difficult to handle and easily fractured. Using off-axis STIM imaging and line scanning over this mask, the NUS nuclear microscope facility has demonstrated beam spot sizes less than 130 nm for a 1 pA 2 MeV proton beam.

Brookhaven National Laboratory electron beam test stand

The main purpose of the electron beam test stand (EBTS) project at the Brookhaven National Laboratory is to build a versatile device to develop technologies that are relevant for a high intensity electron beam ion source (EBIS) and to study the physics of ion confinement in a trap. The EBTS will have all the main attributes of EBIS: a 1-m-long, 5 T superconducting solenoid, electron gun, drift tube structure, electron collector, vacuum system, ion injection system, appropriate control, and instrumentation. Therefore it can be considered a short prototype of an EBIS for a relativistic heavy ion collider. The drift tube structure will be mounted in a vacuum tube inside a “warm” bore of a superconducting solenoid, it will be at room temperature, and its design will employ ultrahigh vacuum technology to reach the 10−10 Torr level. The first gun to be tested will be a 10 A electron gun with high emission density and magnetic compression of the electron beam.

A combined objective lens-energy analyser for electron beam testing of IC

A combined objective lens-energy analyser for electron beam testing of IC

Loading nature of the interfacial cracks in a joint component under fusion-relevant thermal loads

One of the standard design concepts for divertor components in a fusion reactor is the bonded joint structure. Understanding the loading nature of interfacial cracks are significant for the assessment of structural integrity of divertor joint components. In this paper, the thermomechanical loading nature of interfacial cracks is discussed. A bi-material joint element consisting of the CFC/TZM system is considered. A typical fusion operation condition is simulated assuming a pulsed high heat flux loading. Stress singularities near the interfacial crack tips are characterized quantitatively in terms of the fracture mechanical parameters. The evolution of the stress intensity factors and the energy release rate during the given transient thermal load are determined. The difference in loading characteristics between the edge crack and the center crack is discussed. High heat flux cycling tests are performed on brazed CFC/TZM divertor elements in an electron beam test facility. The microstructures of the damaged interface agree with the predicted fracture modes. The loading nature and possible failure mechanisms are discussed for a fusion-relevant thermal loading.

Thermomechanical behavior of actively cooled, brazed divertor components under cyclic high heat flux loads

Actively cooled divertor mock-ups consisting of various low- Z armor tiles brazed to refractory metal heat sinks were tested in the electron beam test facility at Jülich. Screening and thermal cycling tests were perfomed on the mock-ups to estimate the overall thermal performance under cyclic high heat flux (HHF) loadings. By detecting the temperature of the armor surface and the braze layer, it was possible to assess the heat removal capability and the accumulation of interfacial damage. Microstructures were investigated to elucidate the degradation of the joints. Finite element analyses are carried out for the simulated HHF test conditions. Temperature fields and thermal stresses are calculated for a typical divertor module. The nature of thermomechanical behavior of the divertor mock-ups under cyclic HHF loadings is discussed.

Low cycle thermal fatigue testing of beryllium

A novel technique has been used to test the relative low cycle thermal fatigue resistance of different grades of US and Russian beryllium, which is proposed as plasma facing armor for fusion reactor first wall, limiter and divertor components. The 30 kW electron beam test system at Sandia National Laboratories was used to sweep the beam spot along one direction at 1 Hz. This produces a localized temperature `spike' of 750°C for each pass of the beam. Large thermal stresses in excess of the yield strength are generated, due to very high spot heat flux, 250 MW m −2. Cyclic plastic strains on the order of 0.6% produced visible cracking on the heated surface in less than 3000 cycles. An in-vacuo fiber optic borescope was used to visually inspect the beryllium surfaces for crack initiation. Grades of US beryllium tested included: S-65C, S-65H, S-200F, S200F-H, SR-200, I-400, extruded high purity, HIP′d spherical powder, porous beryllium (94 and 98% dense), Be/30% BeO, Be/60% BeO, and TiBe 12. Russian grades included: TGP-56, TShGT, DShG-200, and TShG-56. Both the number of cycles to crack initiation and the depth of crack propagation, were measured. The most fatigue resistant grades were S-65C, DShG-200, TShGT and TShG-56. Rolled sheet Be (SR-200) showed excellent crack propagation resistance in the plane of rolling, despite early formation of delamination cracks. Only one sample showed no evidence of surface melting, Extruded (T). Metallographic and chemical analyses are provided. Good agreement was found between the measured depth of cracks and a 2-D elastic-plastic finite element stress analysis.

Automated placement of testing pads for electron-beam observation

A novel testing-pad placement method has been developed to greatly improve the electron-beam testing observability of multi-metal-layer LSIs. The pads consist of such small stacked vias that they can be placed in any unoccupied area of an LSI layout without any change in chip size. The observability is more than 88% for a 0.25um 390kG ASIC with this method.

Experimental investigation into the use of micro-extraction fields for electron beam testing

In the electron beam testing of integrated circuits, local transverse electric fields cause error to voltage measurements. Presently, the solution is to place a 1–5 kV voltage extraction electrode a few millimetres above the specimen. An alternative method is to use a micro-extraction electrode that is of the same size as the structures to be probed. This paper describes an experimental investigation made into several types of micro-extraction layouts, and shows that they can be used to provide reliable voltage contrast measurements.

Dynamic internal testing of CMOS circuits using hot luminescence

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the dynamics of all the gates of the circuit are simultaneously measured. This noninvasive technique can be extended to smaller device size, as well as probing from the backside of the wafer. The optical emission may provide an alternative to electron beam testing for measuring the dynamics of high-speed CMOS circuits.