Recently, there has been active progress in scaling semiconductor devices to reduce delay time and increase yield at the transistor level. However, this advancement is encountering a limitation in physical miniaturization. The monolithic 3D (M3D) integrated device technology is an emerging method to address this issue, which significantly enhances device packing density and minimizes via thickness [1]. One representation method for M3D integration technology involves depositing amorphous silicon (a-Si) onto the pre-existing lower device layer and then subjecting it to a thermal process to crystallize and form the upper active layer [2, 3]. However, achieving a highly crystalline silicon-based upper active layer with high performance necessitates a crystallization process conducted at elevated temperatures ranging from 700 to 900 °C. The primary constraint in achieving M3D integration technology is the requirement to utilize thermal processes below 450 °C to prevent damage to the lower device layer. When employing conventional thermal processes such as furnaces or rapid thermal processing to reach high temperatures, the duration of heat energy application is prolonged, and precise control over the depth of heat treatment becomes challenging. It can lead to thermal damage to the lower device layer. Furthermore, even after undergoing the crystallization process, the direction of crystal growth remains inconsistent, resulting in non-uniform electrical characteristics across different devices. This inconsistency poses challenges in realizing wafer-level M3D integrated device technology.In this work, we propose a method to create a highly crystalline upper active layer without damaging the lower device layer by employing Si-Ge seeds and laser crystallization. Single-crystal Si-Ge seeds, which induce growth in specific crystal orientations during laser crystallization, were formed at a low temperature of 450 °C using the selective etch growth (SEG) method. Following the deposition of 100 nm of a-Si onto the Si-Ge seed, laser crystallization was performed by scanning in a specific direction starting from the seeded area (Fig. 1). The laser used was a continuous wave (CW) laser with a wavelength of 532 nm. A flat-top line beam shape was utilized to ensure consistent crystallization across the irradiated region [4].As a result, the laser aimed at the seed area melts the interface between Si-Ge and a-Si. Subsequently, Si crystallization occurs following the atomic arrangement of single crystal Si-Ge during the cooling process [4]. The Si-Ge seed and the crystallized Si exhibited crystallinity with the same [110] orientation from transmission electron microscope (TEM) and fast Fourier transform (FFT) pattern analysis (Fig. 2). Following laser scanning in a specific direction, a long single-orientation Si crystal with a length of approximately 15 μm was obtained, preserving the specific crystallinity established from the seed. However, electron backscatter diffraction (EBSD) analysis confirmed that the flat-top line beam, larger than the 2 μm seed area, led to nucleation and crystal growth beyond the intended seed area at a-Si film. This resulted in collisions with grains originating from the seed (Fig. 3). We used a rectangular pattern to reduce nucleation in non-seed regions and prolong crystallization duration. Using this pattern, we successfully formed a single crystal active layer measuring 5 μm in width and 15 μm in length (Fig. 4).In conclusion, we successfully created a single crystal upper active layer using Si-Ge seed-based laser crystallization, a low-temperature process suitable for M3D integration structures. This crystallization method can be extended to create highly crystalline active layers in all layers by consistently generating single crystal seeds capable of inducing high crystallinity in each upper layer when stacking multiple layers in an M3D integrated structure.This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Ministry of Science and ICT (MSIT) (RS-2023-00257003).[1] Y. Cheng et al., Integration, 85, 97-107 (2022)[2] A. H. T. Nguyen et al., Nano Convergence, 11(1), 5 (2024)[3] C. C. Yang et al., Japanese Journal of Applied Physics, 57(4S), 04FA06 (2018)[4] J. Baek et al., Applied Surface Science, 609, 155368 (2023) Figure 1
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Jan 1, 2025
Jinta Arakawa + 4
Just Published
Open Access