Electromigration In Interconnects Research Articles

An electro-thermo-mechanical coupling phase-field model of defect evolution induced by electromigration in interconnects

In this paper, the defect evolution caused by electromigration induced surface diffusion in interconnects is investigated using a newly-developed electro-thermo-mechanical coupling phase-field model. The Joule heat and its resulting thermomigration are included into the phase-field model. The governing equation of the phase-field is solved by semi-implicit spectral methods and the accompanied governing equations of applied physics fields are solved by finite volume methods. Comparative investigation into defect evolution with and without the influence of Joule heating is conducted. It is deduced that thermomigration facilitates local elongation of the defect in the “current crowding” region and exerts a substantial influence on the defect morphological evolution. Subsequently, the effect of the inclination angle of the electric field on the void morphology evolution and crack propagation is discussed. We find that the defect achieves the largest characteristic length when the electric field direction is perpendicular to the uniaxial tension direction, implying a higher threat to the circuit safety. This study may help to deepen people's understanding of how the thermal effect functions in electromigration process and sheds light on different modes of defect evolution in interconnects.

High-frequency characteristics of multilayer graphene nanoribbon interconnects: Exploring the implications OF SKIN effect

A study is undertaken to explore the frequency-dependent traits of crosstalk delay (X-D), crosstalk noise area (X-NA), and the mean time to failure induced by electromigration (EM-MTF) in interconnects constructed from lithium-doped multilayer graphene nanoribbon (Li-MLGNR) and their optimized counterparts, known as optimized Li-MLGNR (O-LiMLGNR) interconnects. The analysis is based on the skin depth and impedance model incorporating scatterers and the finite thickness of the interconnect. The obtained high-frequency impedance and performance characteristics reveals that O-LiMLGNR outperforms Li-MLGNR, rough copper, and mixed carbon nanotube bundle in terms of X-D, X-NA, and EM-MTF. Subsequently, the performance of O-LiMLGNR, limited by process and temperature variations, is analyzed at high frequencies under the influence of skin-effect. As a result of variations in process parameters and temperature, the O-LiMLGNR exhibits an increase in variations of X-D and X-NA, accompanied by a reduction in variation of EM-MTF as the frequency increases.

Study on Phase Electromigration and Segregation Behavior of Cu-Cored Sn-58Bi Solder Interconnects under Electric Current Stressing

Cu-cored solder interconnects have been demonstrated to increase the performance of interconnect structures, while the quantitative understanding of the effect of the Cu-cored structure on microstructure evolution and atomic migration in solder interconnects is still limited. In this work, the effect of the Cu-cored structure on phase migration and segregation behavior of Sn-58Bi solder interconnects under electric current stressing is quantitatively studied using a developed phase field model. Severe phase segregation and redistribution of Bi-rich phase are observed in the Cu-cored Sn-58Bi interconnects due to the more pronounced current crowding effect near the Cu core periphery. The average current density and temperature gradient in Sn-rich phase and Bi-rich phase decrease with an increase in the diameter of the Cu core. The temperature gradient caused by Joule heating is significantly reduced owing to the presence of the Cu core. Embedding of the Cu core in the solder matrix could weaken the directional diffusion flux of Bi atoms, so that the enrichment and segregation of the Bi phase towards the anode side are significantly reduced. Furthermore, the voltage across the solder interconnects is correspondingly changed due to the phase migration and redistribution.

Statistical study of electromigration in gold interconnects

During operation of integrated circuits, electromigration gradually degrades the metallic interconnects, eventually leading to complete failure. In recent decades, electromigration has been studied mainly for the widely used aluminum and copper interconnects, however, gold interconnects used for GaAs devices also experience significant electromigration degradation. We present physics-based modeling and simulation of electromigration in gold interconnects. A comprehensive analysis of the statistical properties of electromigration failure and the influence of varying temperature and geometric properties is performed. The previously published experimental observations on the behavior of the mean failure time and the associated standard deviation are in agreement with the obtained simulation results. In particular, the simulation reproduces an 85% decrease of the standard deviation for a via surface of 31.36μm2 compared to the value for a via surface of 6.76μm2.

Shell effects and free-electrons in electromigrated oxidized Cu-nanocontacts

Electromigration in interconnects continues to be an important field of study in integrated circuits as the interconnects are planned to shrink in size at comparable pace as the semiconductor functional elements. Through shrinking the interconnects approach the regime where quantum size effects become important. The observation of quantum size and shell effects is usually restricted either to low-temperatures or vacuum conditions or to chemically inert materials such as Au. Here, we show that in electromigrated Cu nanocontacts such effects can be observed at room temperature and room pressure even in the presence of oxidation. Our data provide evidence that the nanocontacts are nearly spherical objects with a triangular-cylindrical symmetry of their electronic wave functions with a stronger free-electron-like character compared to previous results. We do not observe a detrimental effect of oxygen. The presence of shell effects has implications for the technological use of Cu nanocontacts as interconnects in integrated circuits and could lead to the use of electronic wave functions of shells in such interconnects.

(Invited) Electrochemical Metallization For Semiconductor Applications

Initially after the invention of electroplating in 1805 it was mostly for used decorative applications and making printing press plates. But the introduction of copper as a replacement for aluminum as a CMOS interconnect material in 1997 by IBM (1) was a breakthrough in silicon chip manufacturing. The replacement of aluminum by copper not only has the benefit of lower interconnect resistance, but also has enabled improved interconnect reliability. Cu is expected to show better reliability because it has a high melting temperature and much lower grain boundary- and lattice diffusivity than aluminum (2). since electroplating is a low-cost and reliable technique, the method is being used for a wide variety of metal deposition applications in the semiconductor industry that includes interconnect & packaging metallization, and compound semiconductor fabrication for low-cost solar cells. Since the late 1990's, after IBM introduced copper interconnects, the development of the copper damascene process (1,3) and the implementation of the copper-based interconnect has had a considerable impact in the electrochemical society and semiconductor industries. Copper metallization technology has become critical for CMOS back-end interconnect, embedded multi-chip interconnect bridges, and interposers for 2.5D and 3D applications.In this presentation, after a brief discussion of the history of metallization by electrochemistry for semiconductor applications, the development of Copper, Gallium, and Cobalt Metallization will be discussed with their application in the semiconductor technology. The discussion will focus on initial issues that arose and the various directions followed to properly address them. The presentation will then focus on the challenge of barrier and seed step coverage and their impact on defects in Cu damascene metallization. Topics of discussion will include the effect of additives, current density, bath aging, shelf life and their implication on product reliability.References R, Liu, C. Pai and E Martinez " Interconnect Technology Trend for Microelectronics", Solid state Electron. 43, 1003(1999)S. Hau-Riege and C. V. Thomson, " Electromigration in copper interconnects with very different grain structures" Appl. Phys. Lett. 78, 3451 (2001)K. Broadbent, E. J. McInerney, L. A. Gochberg, and R. L. Jackson, " Experimental and Analytical study of seed layer resistance for copper damascene electroplating" J Vac. Sci. Techonl. B17, 2584(1999)

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

The downsizing of integrated circuits for the upcoming technology nodes has brought attention to sub-2 nm thin organic/inorganic materials as an alternative to metallic barrier/capping layers for nanoscaled Cu interconnects. While self-assembled monolayers (SAMs) serving as the barrier materials for copper metalized films are well studied, electromigration (EM) of Cu interconnects encapsulated by SAMs is an untouched research topic. In this study, we report an all-wet encapsulating process involving SAM seeding/encapsulating and electroless narrow-gap filling to fabricate nanoscaled copper interconnects that are completely encapsulated by a 1 nm-thin amino-based SAM, subsequently annealed to some extents prior to EM testing. Both annealing and SAM encapsulation retard EM of the Cu interconnects tested at current densities on orders of 108–109 A cm−2. Particularly, SAM encapsulation quintuples the lifetime of, for example, as-fabricated Cu interconnects from 470 to 2,890 s. Electromigration failure mechanisms are elucidated from analyses of activation energies and current-density scale factors obtained from the accelerated EM testing. The importance of SAM qualities (e.g., ordering and layered structure) as a prerequisite for the reliability enhancement cannot be overestimated, and the results of the SAM quality evaluation are presented. The mechanism of reliability enhancement is also thoroughly discussed.

Thermal-Aware EM Reliability for Advanced Metal Interconnects of Complementary FET

Electromigration (EM) of metal interconnects is the continuous reliability concern for high-density integration beyond 5-nm technology, especially for the buried power rails in vertically stacked device structure. In this work, EM reliability of alternative metal interconnects based on complementary FET (CFET) is investigated by kinetic Monte Carlo (KMC) method. The microscopic evolutions of void formation in power rails can be well reproduced by considering the coupled effects of thermal and stress distribution during the EM simulation. The influences of grain boundary in different metal materials on EM lifetime are analyzed to provide the optimal strategy of process integration. Thermal-aware EM reliability is further predicted, indicating the importance of self-heating on EM evaluation of power rails in CFET.

Hexagonal Boron Nitride: Mitigation of Electromigration in Metal Interconnects via Hexagonal Boron Nitride as an Ångström‐Thin Passivation Layer (Adv. Electron. Mater. 6/2021)

Ångström-thin hexagonal boron nitride (hBN) is a highly promising barrier/liner dielectric material for passivating electrical interconnects in ultra-scaled integrated circuits (ICs). In article number 2100002, Michael Cai Wang and co-workers present a novel approach to mitigating electromigration in nanoscale copper interconnects. Significant improvements in the breakdown current density and operating lifetime are observed in hBN-passivated copper interconnects, paving the way for further single-nanometer node scaling of semiconductor and ICs manufacturing

Mitigation of Electromigration in Metal Interconnects via Hexagonal Boron Nitride as an Ångström‐Thin Passivation Layer

AbstractElectromigration in metal interconnects remains a significant challenge in the continued scaling of integrated circuits towards ever‐smaller single‐nanometer nodes. Conventional damascene architectures of barrier/liner layers and conducting metal cause inevitable compromises between device performance and feature dimensions. In contrast to contemporary barrier/liner materials (e.g., Co, Ta, and Ru), an ultrathin passivation layer that can effectively mitigate electromigration is needed. At the ultimate atomically‐thin limit, 2D materials are promising candidates given their exceptional mechanical properties and impermeability. Here, a facile and effective approach is presented to mitigating electromigration in copper (Cu) interconnects via passivation with insulating monolayer 2D hexagonal boron nitride (hBN). The hBN‐passivated Cu interconnects, compared to otherwise identical but bare Cu interconnects, exhibit on average a >20% higher breakdown current density and a >2600% longer lifetime (at a high current density of 5.4 × 107 A cm−2). Post‐mortem metrology elucidates uniform conformal contact between the hBN‐passivated Cu interface and common failure features due to electromigration.

A phase field computational procedure for electromigration with specified contact angle and diffusional anisotropy

Electromigration in electrical interconnects with high current density causes voids to form and grow near the cathode. These voids can possibly grow large enough to cause open circuit failure. The simulation of electromigration void nucleation and growth is challenging because of the complex interaction of electrical, thermal and mechanical fields that lead to the observed voids. In this paper, a phase-field approach is developed to study void growth due to electromigration taking into account diffusional anisotropy and specified contact angle. Consideration of anisotropy and contact angle is critical in applications including electronic assemblies that most commonly use Sn-based solder interconnects. In such systems, Sn exhibits significant anisotropy in its self-diffusivity, which assumes importance in small solder joints that are known to contain only a few grains. Furthermore, the contact angle at the void-bonding pad-solder triple junction is known to influence the void size and shape. To the best of the authors’ knowledge, only anisotropy in surface diffusivity has been considered in phase-field electromigration literature, whereas the contact angle at a triple junction has not been considered. The developed phase-field model incorporates effects of both contact angle and anisotropy in self-diffusivity. The model is used to simulate systems with different contact angles and dominant directions of diffusion. It is observed that diffusional anisotropy plays a more dominant role in failure, while the contact angle dictates evolution of the shape of voids.

A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects

Considering temperature gradient or thermomigration (TM) impacts on electromigration (EM) due to Joule heating was less studied in the past. In this article, we propose a new semi-analytical stress transient analysis method to consider both EM and TM effects for general multisegment interconnects. The new method is based on the separation of variables (SOVs) approach to find the analytic solution of coupled EM-TM partial differential equation (PDE). The algorithm consists of several steps. We first develop analytic solutions to compute the steady-state temperature distribution of multisegment wires. Based on this, we derive closed-form solutions for steady-state hydrostatic stress distribution in the context of thermal gradients due to Joule heating for multisegment interconnect wires. With the steady-state stress distribution, the coupled EM-TM PDE can be homogenized and solved by the SOV method. To deal with temperature/position-dependent diffusivity of metal migration process due to nonuniform temperature distribution, we utilize a piecewise linear technique to approximate the position-dependent diffusivity. The numerical results on multisegment interconnects show that the proposed method has negligible error loss compared to commercial finite element analysis software COMSOL but is about an order of magnitude faster than COMSOL with $10\times $ less memory footprint. The numerical results further show that temperature gradient due to Joule heating indeed has significant impacts on the EM failure process.

Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip

In this article, we will present recent advances in VLSI reliability effects with a focus on electromigration (EM) failure/aging effect on interconnects, which is one of the most important reliability concerns for VLSI systems especially at the nanometer regime. One of the most important advances for EM analysis in recent years is the recognition that EM failure analysis can't depend on single wire segment anymore, as done in the traditional Black and Blech's based methods. New generation of EM modeling and design must consider all the wire segments in an interconnect as the hydrostatic stress in those wire segments affect each other. Such recognition bring both challenges and opportunities. We will start with physics-level stress-oriented characterization of EM failure effects and recently proposed three-phase EM models. Then we present a new EM immortality check at the circuit level considering multi-segment interconnects and void saturation volumes. After this, we will present how to accelerate EM aging effects for fast EM validation at the circuit level under normal working conditions using advanced structure-based techniques. Finally, we will present new EM sign-off analysis tool, called EMspice, at the full-chip power grid level considering the interplays between resistance changes from post-voiding processes and current density changes from power grids over the aging process. A number of other relevant works will be reviewed and compared as well.

Numerical Modelling of Interconnect Electromigration Under Non-DC Stressing Conditions

A numerical model of the equivalent time conversion to DC stressing for electromigration failures under various current waveforms is proposed based on the vacancy diffusion and damage healing theory. The Joule heating effect and the intrinsic stress-induced voiding are included in the calculation of interconnect reliability. The simulation results show that the cumulative lifetimes are strongly affected by current frequency and vacancy lifetime and a frequency shift to the right occurs for small vacancy lifetimes under AC stressing. For pulsed-DC stressing, the temperature rise dependent on the current frequency dominates the interconnect reliability. The average temperature rise due to Joule heating is reduced by two times when the frequency is larger than approximately the reciprocal of the thermal time of interconnect structures.

Pulse electrodeposition of copper-manganese alloy in deep eutectic solvent

Copper-manganese alloy has been established to improve resistance toward electromigration for interconnects. In this work, we employ a deep eutectic solvent (DES) to formulate a nonaqueous electrolyte for pulse current electrodeposition of Cu-Mn alloyed film. Using impedance spectroscopy to record ionic conductivities of DES-based electrolytes, we determine the optimized bath with a Cu/Mn molar ratio of 1:20. We produce an uniform, smooth, and composition-controllable CuMn alloyed film after exploring various pulsing parameters. Signals from X-ray diffractometer (XRD) suggest successful alloying of Cu and Mn with minor presence of MnO2. Profiles from X-ray photoelectron spectroscopy (XPS) validate the metallic nature of Mn from the as-deposited film. Upon Ar annealing, both XRD and XPS exhibit strong signals of MnO2 formation. In addition, images from transmission electron microscope and qualitative elemental chemical mapping indicate Mn atoms in CuMn alloy either diffuse through the underlying Cu seed layer and segregate at the Cu/SiO2 interface, or migrate toward the external surface forming MnO2.

Effects of β-Sn grain c-axis on electromigration behavior in BGA Sn3.0Ag0.5Cu solder interconnects

The anisotropy of β-Sn grain can significantly affect the electromigration (EM) behavior in Sn3.0Ag0.5Cu (SAC305) solder interconnects. A real ball grid array (BGA) specimen with a cross sectioned edge row suffered electromigration for 600 h to investigate the effects of β-Sn c-axis on the behavior of electromigration in SAC305 solder interconnects. Scanning electron microscopy (SEM) and electron backscattered diffraction (EBSD) were used to obtain the microstructure and orientation of β-Sn grains in as-reflowed and low current density conditions. Besides, the orientation of c-axis had a great effect on the growth direction of IMCs in solder matrix. The solder interconnect with the Sn grain c-axis pointing the positive direction of ND would emerge serious electromigration phenomena. The density of Cu6Sn5 IMCs distributing at the surface of solder matrix increased obviously. However, when Sn grain c-axis was in the same direction with the opposite direction of ND, the original Cu6Sn5 IMCs in as-reflowed solder interconnect disappeared. Therefore, the results show that the solder interconnects will performance a different electromigration behavior due to the direction of c-axis in Sn grain: the growth direction of Cu6Sn5 IMCs in solder matrix will along the c-axis accompanied growing into solder matrix or gathering at the surface of the cross section.

Phase-Field-Crystal Model for Electromigration in Metal Interconnects.

We propose an atomistic model of electromigration (EM) in metals based on a recently developed phase-field-crystal (PFC) technique. By coupling the PFC model's atomic density field with an applied electric field through the EM effective charge parameter, EM is successfully captured on diffusive time scales. Our framework reproduces the well-established EM phenomena known as Black's equation and the Blech effect, and also naturally captures commonly observed phenomena such as void nucleation and migration in bulk crystals. A resistivity dipole field arising from electron scattering on void surfaces is shown to contribute significantly to void migration velocity. With an intrinsic time scale set by atomic diffusion rather than atomic oscillations or hopping events, as in conventional atomistic methods, our theoretical approach makes it possible to investigate EM-induced circuit failure at atomic spatial resolution and experimentally relevant time scales.

Airgaps in nano-interconnects: Mechanics and impact on electromigration

In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

Analysis of the Impact of Variations on Signal Electro-Migration and Optimization of Interconnects in FinFET Designs.

The An AC current induced electro-migration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyze EM on signal interconnects in 16 nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. We also analyze signal-line EM with transistor-level PVT (process-voltage-temperature) variation corners. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16 nm design.

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about $2.5 {\times }$ – $161 {\times }$ by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.