Electromigration Failure Rate Research Articles

Electromigration Effects in Power Grids Characterized From a 65 nm Test Chip

A 65 mn test chip to study electromigration (EM) events in integrated circuit power grids was taped-out and successfully tested. A $9\times 9$ grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the DUT temperature to 350°C without damaging the peripheral circuitry and chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could directly observe for the first time, the voltage drop map across the entire power grid. Subtle changes on the monitored voltage map uncovered mechanical stress dependent failure locations as well as self-healing due to redundant current paths. The EM failure rate and order of failure locations were also analyzed.

Electrical and Thermal Co-Design for High-Power FPGA Packages

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multihundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal co-design to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications.

The effect of contact resistance on current crowding and electromigration in ULSI multi-level interconnects

Electromigration (EM) has been the most persistent interconnect reliability issue over the decades. In general, EM damages tend to occur at atomic flux divergence sites. The EM failure rate can be further accelerated by current crowding, which occurs when current flows between inter-level wires. In this work, we used two different via etch schemes to study the effect of contact resistance on current crowding and EM. We found that the etch stop structures show longer EM lifetimes than the over etch. The contact resistance of the etch stop is higher than that of the over etch. Two-dimensional simulation results show that the higher contact resistance in the etch stop can suppress current crowding and improve EM lifetimes. Differences in void morphology between the over etch and etch stop as a result of current crowding are discussed.

The effects of microstructural transitions at width transitions on interconnect reliability

Interconnect reliability is usually assessed through lifetime tests on straight stud-to-stud lines with fixed widths. However, real interconnects often have junctions with narrow-to-wide transitions. We have carried out experimental and modeling-based studies of interconnects with narrow-to-wide transitions to test the Korhonen model for electromigration-induced failure and determine parameters for failure. Two-level Al-0.5% Cu via-to-via electromigration test structures with narrow-to-wide width transitions have been studied as a function of the ratio of linewidths and as a function of the ratio of lengths of the wide and narrow line segments. The narrow-to-wide transition was found to be a site of atomic flux divergence due to the discontinuity in diffusivities between the narrow and wide segments, which have bamboo and polygranular microstructures, respectively. Consequently, it was found that the electromigration failure rate increases as the position of width transition is decreased below a critical distance from the electron–source via. This occurs due to an interaction between evolution of the stress field at the electron–source via and the evolution of the stress field at the width transition. Narrow-to-wide transitions with positions greater than a critical distance from the electron–source via have much higher lifetimes which are not a function of the transition location, due to a lack of interaction between the electron–source via and the width transition. Because the mode of failure was identical for all structures (i.e., failure by voiding at the electron–source via), use of experimental results with simulations allows determination that the critical stress range for void-nucleation failure in these structures is 600 MPa±108. It was experimentally found that changing linewidth ratios did not affect interconnect reliability when the transition was 150 μm away from the electron–source via. However, simulations indicate that if the width transition is close to the electron–source via, the lifetime should decrease with the width of the polygranular region. Additional electromigration studies have been conducted on constant-width interconnects in which microstructural transitions were created using a scanned laser annealing. Analyses of the experiments are consistent with those on microstructural transitions caused by width transitions.

The Effects of Width Transitions on the Reliability of Interconnects

AbstractExperimental and modeling studies of Al-based interconnects with narrow-to-wide transitions show that the width transition is a site of atomic flux divergence due to the discontinuity in diffusivities between the narrow and wide segments, which have different microstructures. Lifetimes have been experimentally determined for populations of lines with width transitions, which have varying line-width ratios and varying locations of the width transitions with respect to the line end. The electromigration failure rate is increased as the width-transition is moved closer to the electron-source via. Correlation of the effects width transitions on lifetimes allows determination of the critical stress range for void -nucleation failure, which was found to be 600 ± 108 MPa.

Simulation of the effects of grain structure and grain growth on electromigration and the reliability of interconnects

Electromigration-induced failure of on-chip interconnects continues to be a problem for the microelectronics industry. The electromigration failure rate of a population of similar lines is sensitive to statistical variation in the microstructural characteristics from line to line. These microstructural details depend upon the process and thermal history of the line as well as on the feature size (line length and width). Moreover, as the widths of interconnect lines have fallen below the median grain size of the films from which they are patterned, two distinct types of failure mechanisms have been observed. Determining which failure mechanism(s) will be observed, and in what proportion, is a crucial concern of reliability engineers. This article investigates the complex dependence of the dominant failure mechanism and overall reliability on process history, minimum feature size, line type, line microstructure, and line test conditions. A grain growth simulator has been used to model the microstructural evolution of a film during processing, both prior to and after patterning. In this fashion, large populations of lines with realistic microstructures have been generated in order to observe statistical differences in microstructure and failure rate. An electromigration model is then used to calculate stress evolution. By assuming a critical stress at which the line fails, the failure distributions and overall reliability of the interconnects are obtained, and the conditions under which a transition-in-failure mechanism will occur are predicted.

A current waveform simulator using charge‐based current model

Abstract Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drops, etc. A new current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: (1) Differential gate capacitor currents, (2) charging currents for load capacitance, and (3) short‐circuit currents. The first one occurs when input changes and the others exist only when the output changes. Hence this model can generate negative current waveform, like SPICE. These three components are characterized with triangular functions with four parameters which can be easily obtained after a timing simulation. This model can be used in any switch‐level timing simulators to generate current waveforms. The simulated current waveform, instead of the average estimation, helps solve VLSI reliability problems due to the electromigration and excess voltage drops in the power buses. When comparing the results obtai...

The applicability of logarithmic extreme value distributions in electomigration induced failures of [formula omitted] thin-film interconnects

In electromigration failure studies it is in general assumed that electromigration induced failures may be adequately modelled by a log normal distribution. Further to this it has been argued that a log normal distribution of failure times is indicative of electromigration mechanisms. We have combined post processing of existing life-data from Al Cu+ TiW bilayer interconnects with our own results from Al Cu interconnects to show that the Log Extreme Value distribution is an equally good statistical model for electromigration failures, even in cases where grain size exceeds the line width. The significance of such a modelling is particularly apparent in electromigration failure rate prediction.

Comparative Study of Statistical Distributions in Electromigration-Induced Failures of Al/Cu Thin-Film Interconnects

In electromigration failure studies, it is in general assumed that electromigration-induced failures may be adequately modelled by a log-normal distribution. Further to this, it has been argued that a lognormal distribution of failure times is indicative of electromigration mechanisms. We have combined post processing of existing life-data from Al/Cu + TiW bilayer interconnects with our own results from Al/Cu interconnects to show that the Log Extreme Value distribution is an equally good statistical model for electromigration failures, even in cases where grain size exceeds the linewidth. The significance of such a modelling is particularly apparent in electromigration failure rate prediction.

Circuit reliability simulator for interconnect, via, and contact electromigration

A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>