Electromigration Effects in Power Grids Characterized From a 65 nm Test Chip

Abstract

A 65 mn test chip to study electromigration (EM) events in integrated circuit power grids was taped-out and successfully tested. A $9\times 9$ grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the DUT temperature to 350°C without damaging the peripheral circuitry and chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could directly observe for the first time, the voltage drop map across the entire power grid. Subtle changes on the monitored voltage map uncovered mechanical stress dependent failure locations as well as self-healing due to redundant current paths. The EM failure rate and order of failure locations were also analyzed.