Electrostatic Discharge Protection Applications Research Articles

Compact and Low Leakage Devices for Bidirectional Low-Voltage ESD Protection Applications

In advanced charged device model (CDM) protection engineering, it is necessary to provide dedicated dual-directional electrostatic discharge (ESD) protection between input/output (I/O) and ground (GND) to discharge the large amount of charge stored in the silicon substrate efficiently. This letter presents two improved bidirectional and low-voltage silicon-controlled rectifiers (BLVSCR-type1 and BLVSCR-type2), which are composed of two diode-triggered SCRs of opposite polarity in parallel. By improving the device structure and metal connection, the BLVSCR-type1 and BLVSCR-type2 can offer robust ESD capabilities. Compared with the conventional bidirectional direct-connected SCR (BDCSCR), experimental results show that the proposed BLVSCR-type1 can render a three order of magnitude reduction in the leakage current at a 1.2V I/O port and more stable parasitic capacitance characteristic. Moreover, the BLVSCR-type2 can possess a compact layout area reduced by as much as 35% when comparing to BLVSCR-type1.

Bidirectional silicon‐controlled rectifier for advanced ESD protection applications

In this Letter, an enhanced bidirectional modified lateral silicon-controlled rectifier (EBMLSCR) is proposed for advanced dual-directional electrostatic discharge (ESD) protection applications. The ESD characteristics of the novel EBMLSCR and conventional bidirectional modified lateral silicon-controlled rectifier (BMLSCR) are measured using the transmission line pulsing tester. Compared with the BMLSCR, the EBMLSCR owns a lower trigger voltage down to 7.7 V, a higher failure current up to 6.5 A, a suitable holding voltage as well as the same superior leakage current. Based on these advantages, the proposed EBMLSCR can provide an effective ESD protection for the advanced 2.5 V/3.3 V input/output circuits, while the traditional BMLSCR becomes invalid for these applications due to its high trigger voltage and low robustness. In addition, the impact of some critical dimensions of the EBMLSCR has also been evaluated to further optimise the device performances.

A Low-Capacitance and Fast-Response Bidirectional SCR for RFICs ESD Protection Applications

For the radio frequency integrated circuits (RFICs) electrostatic discharge (ESD) protection special applications, a novel low-capacitance and fast-response bidirectional silicon controlled rectifier (LFBSCR) is developed. The low capacitance is achieved by changing the series-parallel relationship of parasitic capacitances located in the electrostatic discharge path. Moreover, the fast-response-time (Ton) and the low triggering voltage (Vt1) parameters are obtained due to gate-assistant triggering mechanism. The experimented results show excellences of the LFBSCR in ESD protection critical performance: low parasitic capacitance CESD~100fF, fast effective response Ton~100ps, low triggering voltage Vt1~4.06V, and low leakage current Ileak~0.016nA. With aforementioned excellences, a high rbustness, and a small ESD design windows, the proposed LFBSCR is very suitable for RFICs ESD protection applications.

Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection

Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P− implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P−/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge (ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor (CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor (GGNMOS) transistor triggered silicon-controlled rectifier (SCR) structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

Silicon-Controlled Rectifier for Electrostatic Discharge Protection Solutions With Minimal Snapback and Reduced Overshoot Voltage

An electrostatic discharge (ESD) protection structure constructed by the stacking of multiple anode gate–cathode gate directly connected silicon-controlled rectifiers (DCSCRs), fabricated in a 0.18- $\mu \text{m}$ CMOS technology is reported in this letter. Two embedded diodes in the DCSCR dictate the turn-ON mechanism and hence give rise to a trigger voltage equal to twice the diode’s turn-ON voltage. This approach enables the DCSCR to offer a diode-like transmission line pulsing IV characteristic with a minimal snapback and a SCR-like high-ESD robustness. At 25 °C, DCSCR has an acceptable nanoampere-level leakage current. Besides, it is verified that the DCSCR can significantly reduce overshoot voltage when stressed by very-fast-rising pulses. As such, an ESD clamp constructed by stacking a selected number of DCSCRs can offer a flexible trigger/holding voltage and is suitable for low and medium voltage ESD protection applications.

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal–oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal–oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications

In this paper, an optimized pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) fabricated in a 0.18- \(\mu \) m CMOS technology is proposed as a viable electrostatic discharge (ESD) protection solution. Capable of working under both the power-ON and power-OFF conditions, this structure is verified to provide bidirectional ESD protection performance superior to those reported in the literatures. Critical ESD parameters, such as the trigger voltage, holding voltage, and leakage current, can be flexibly adjusted via layout changes. With a low trigger voltage, a small ESD design window, a high robustness, and a small silicon area consumption, the PTBSCR is very suitable for low-voltage and low-power ESD protection applications.

A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection

The turn-on speed of electrostatic discharge (ESD) protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device (DTSCR) can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p–n–p and n–p–n transistors. Using the variation lateral base doping (VLBD) structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure (VLBD_DTSCR) is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD_DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n–p–n and p–n–p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD_DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.

ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications.

Minimizing Multiple Triggering Effect in Diode-Triggered Silicon-Controlled Rectifiers for ESD Protection Applications

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCR's turn-on characteristic is also discussed.

A novel power-clamp assisted complementary MOSFET for robust ESD protection

A novel power-clamp assisted complementary MOSFET (PCACMOS), modified from traditional gate-coupled complementary MOSFET (GCCMOS), is proposed for high robust ESD (Electrostatic discharge) protection application. The power-clamp achieves by RC-NMOS and designs by Spice simulation. The comprehensive performance of the protection schemes are evaluated by the figure of merit (FOM). Compared with traditional gate-coupled MOSFET (GCCMOS) protection scheme, the power-clamp assisted complementary MOSFET (PCACMOS) protection scheme has a similar turn-on speed but higher FOM.

Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors

Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-to-gate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.

Investigation of diode geometry and metal line pattern for robust ESD protection applications

The effect of different diode geometries and metal patterns on the failure current It2 is investigated experimentally. The devices considered are N+/P well LOCOS diodes having different lengths, widths, finger numbers, and metal connections. The results provide useful insights into optimizing the diode for robust electrostatic discharge (ESD) protection applications.

An Improved Bidirectional SCR Structure for Low-Triggering ESD Protection Applications

An improved dual-polarity silicon-controlled rectifier (SCR) device has been proposed and realized in a 0.6-mum bipolar complementary metal-oxide-semiconductor process. The device can be used to protect electrostatic discharge (ESD) in both the positive and negative directions on pins with a voltage range that goes below ground. Comparing with the conventional bidirectional SCR structures, the new device is more suitable for low-voltage integrated circuit ESD protection applications because it possesses a smaller trigger voltage, a smaller leakage current, and a larger holding voltage.

A robust polysilicon-assisted SCR in ESD protection application

A novel polysilicon-assisted silicon-controlled rectifier (SCR) is presented and analyzed in this paper, which is fabricated in HHNEC’s 0.18 μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help by pass electro-static discharge (ESD) current without occupying extra layout area. TLP current-voltage (I-V) measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR’s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 μm2 layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.