Electrostatic Discharge Noise Research Articles

Accurate and Efficient Computation of System-Level ESD Noise Waveforms in ISO 10605 Standard Using Decomposition Method and Split-Domain Approach

In this article, an accurate and efficient computational method of system-level electrostatic discharge (ESD) noise waveforms in a field-coupled ESD test of the ISO 10605 standard using a 3-D full-wave solver is proposed. To apply efficient computational methods to the ESD test simulation, the split-domain approach and decomposition method are first individually validated with a simple structure. Next, a method simultaneously using the decomposition method and split-domain approach is proposed and validated with the separately given field source data. Using the proposed method with the measured electromagnetic fields radiated from an ESD generator, the ESD noise waveforms in the ISO 10605 field-coupled ESD test are accurately and efficiently computed by considering not only the ESD current coupling but also the radiated coupling from the ESD generator.

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

Fast and Accurate Calculation of System-Level ESD Noise Coupling to a Signal Trace by PEEC Model Decomposition

A fast and accurate calculation method of system-level electrostatic discharge (ESD) noise coupling based on model decomposition of the partial element equivalent circuit is proposed. The proposed method can significantly reduce the calculation time without loss of accuracy by separating small victim signal traces from large aggressor structures such as ground planes and ESD gun strap. Using the method, the ESD noise coupling at the terminations of a victim signal trace is rigorously calculated and validated with measurements and full-wave simulations in both frequency and time domains.

How to defeat electrostatic discharge

The generation of electrostatic discharge (ESD) and the ways in which it causes failure are explained. Three ways of solving ESD problems are described and evaluated. They are: preventing ESD altogether; preventing the coupling of ESD noise into circuits or devices; and increasing the inherent noise immunity of devices and circuits. Firmware and software solutions to ESD upsets are also considered, and ESD testing is discussed. >