Electrochemical Etch-stop Technique Research Articles

In-tube micro-pyramidal silicon nanopore for inertial-kinetic sensing of single molecules

Electrokinetic force has been the major choice for driving the translocation of molecules through a nanopore. However, the use of this approach is limited by an uncontrollable translocation speed, resulting in non-uniform conductance signals with low conformational sensitivity, which hinders the accurate discrimination of the molecules. Here, we show the use of inertial-kinetic translocation induced by spinning an in-tube micro-pyramidal silicon nanopore fabricated using photovoltaic electrochemical etch-stop technique for biomolecular sensing. By adjusting the kinetic properties of a funnel-shaped centrifugal force field while maintaining a counter-balanced state of electrophoretic and electroosmotic effect in the nanopore, we achieved regulated translocation of proteins and obtained stable signals of long and adjustable dwell times and high conformational sensitivity. Moreover, we demonstrated instantaneous sensing and discrimination of molecular conformations and longitudinal monitoring of molecular reactions and conformation changes by wirelessly measuring characteristic features in current blockade readouts using the in-tube nanopore device.

A Low-Power Robust Humidity Sensor in a Standard CMOS Process

This paper presents a low-cost thermal-conductivity-based humidity sensor implemented using a 0.6-mum CMOS process, where suspended p-n junction diodes are used as the humidity-sensitive elements. The measurement method uses the difference between the thermal conductivities of air and water vapor at high temperatures by comparing the output voltages of two heated and thermally isolated diodes; one of which is exposed to the environment and has a humidity-dependent thermal conductance, while the other is sealed and has a fixed thermal conductance. Thermal isolation is obtained by a simple front-end bulk silicon etching process in a TMAH solution, while the diodes are protected by the electrochemical etch-stop technique. The suspended diodes are connected to an on-chip circuit using polysilicon interconnect layers in order to increase their thermal resistance to be able to heat them with less power. Due to the high electrical resistance and positive temperature coefficient of resistance of the polysilicon, temperature sensitivities of the diodes are reduced to -1.3 mV/K at a 100-muA bias level. The diodes and the readout circuit are monolithically integrated using a standard 0.6-mum CMOS process. Characterization results show that humidity sensitivity of the sensor is 14.3, 26, and 46.9 mV/%RH for 20degC, 30degC, and 40degC, respectively, with a nonlinearity less than 0.3%. Hysteresis of the sensor is less than 1%. The chip measures 1.65 mm times 1.90 mm, operates from a 5-V supply, and dissipates only 1.38-mW power.

Fabrication of Pressure Sensors with Diaphragm by Electro-Chemical Etch-Stop

A diaphragm, the most important part of pressure sensor, was successfully fabricated by an electro-chemical etch-stop (ECES) technique. It was important to control the thickness of the diaphragm precisely. We compared characteristic results of diaphragms by electro-chemical etch-stop with those by time-control etch-stop (TCES). The 4 inch n-Epi/p-substrate with 16±1 ㎛ thickness was utilized because the thickness of the diaphragm fabricated by ECES is controlled by the thickness of Epi.. The etching of silicon wafer was carried out in the solution (25 wt% KOH) at 80°C, using 3 electrode system with potentiostat. Proper voltages were applied to etch p/n-type silicon wafer after determined open circuit potential (OCP) and passivation potential (PP) of n and p-type silicon, respectively. Thickness of diaphragms fabricated by ECES was controlled in the range of 16±1 ㎛ while that by TCES was in the range of 16.1±2 ㎛. The roughness of diaphragm was 52±5 Å. When the pressure of 50 kPa was applied on the pressure sensor using the diaphragm fabricated by ECES, the error rate was improved to ±10 ㎷. In the case of the error rate of pressure sensor using the diaphragm fabricated by TC was in the range of ±25 ㎷ under the same condition.

A low-cost uncooled infrared microbolometer detector in standard CMOS technology

This paper reports the development of a low-cost uncooled infrared microbolometer detector using a commercial 0.8 /spl mu/m CMOS process, where the CMOS n-well layer is used as the infrared sensitive material. The n-well is suspended by front-end bulk-micromachining of the fabricated CMOS dies using electrochemical etch-stop technique in TMAH. Since this approach does not require any lithography or infrared sensitive material deposition after CMOS fabrication, the detector cost is almost equal to the CMOS chip cost. The n-well has a TCR of 0.5-0.7%/K, relatively low compared to state-of-the-art microbolometer materials; however, it has negligible 1/f noise due to its single crystal structure. The use of polysilicon interconnects on the support arms instead of metal reduces the overall pixel TCR to 0.34%/K, but provides a better performance due to improved thermal isolation. Based on this pixel, a 16 /spl times/ 16 prototype focal plane array (FPA) with 80 /spl mu/m /spl times/ 80 /spl mu/m pixel size and 13% fill factor has been implemented, where built-in diodes are used to simplify array scanning, at the expense of reduced overall pixel TCR of 0.24%/K. The n-well microbolometer array with a simple readout scheme provides a responsivity of 2000 V/W, a detectivity of 2.6 /spl times/ 10/sup 8/ cmHz/sup 1/2//W, and an estimated NETD of 200 mK at 0.5 Hz frame rate. Considering that this performance can be further improved with low noise readout circuits, the CMOS n-well microbolometer is a cost-effective approach to implement very low-cost uncooled infrared detector arrays with reasonable performance.

Electrochemical etch-stop technique for silicon membranes with p- and n-type regions and its application to neural sieve electrodes

In this study the field effects on electrochemically controlled silicon etching in KOH during three- and four-electrode pn etch-stop have been investigated. When a p-doped bulk area is surrounded by n-doped silicon and the n-doped silicon is electrochemically passivated, small lines of bulk silicon in between the n-doped silicon would not etch. The size of the bulk silicon that did not etch could be moderated by the applied potential on the n-doped silicon during pn etching. For the three-electrode system the size of the electric field passivated bulk silicon could be controlled for line widths ranging between 60 and 100 μm. When a four-electrode system was used and the p-doped bulk silicon was forced to a more negative potential, it was possible to etch lines of bulk silicon down to 40 μm widths. This field-restricted pn etch-stop can be used for fabricating thin membrane structures with densely spaced n-doped regions that can be individually addressed by electronics. One application is the fabrication of neural sieve electrodes which comprise a pn etch-stopped membrane containing several phosphorous-doped individually addressable recording electrodes.

An integrated thermopile structure with high responsivity using any standard CMOS process

This paper reports a new thermopile structure using n-poly/p +-active layers that are available in any CMOS technology. The thermopile structures are obtained by post-etching of the fabricated and bonded chips. P +-active layers are placed in n-well regions, which are protected from etching by the electrochemical etch-stop technique in a TMAH solution. The n-well regions are then removed using a short EDP etching to reduce the thermal conductivity of the suspended structures, improving the responsivity significantly. The characterization results show that Seebeck coefficients of the n-poly and p + -active layers are − 320 ± 15 and 430 ± 20 μV K −1, respectively, resulting in a total Seebeck coefficient of 750 ± 35 μV K −1. A two-arm bridge thermopile test structure results in a responsivity and a detectivity of 49.8 V W −1 and 5.75 × 10 6 cm Hz 1/2 W −1, respectively, in vacuum when the n-well is removed.

Passive and fixed alignment of devices using flexible silicon elements formed by selective etching

Assembly systems consisting of aligning pits combined with flexible holding elements have been produced for both passive and fixed alignment of devices such as chips and optical fibres. The free-standing holding elements were fabricated in bulk silicon using the photovoltaic electrochemical etch-stop technique. The pits were oriented along the direction which resulted in square etch profiles and in underetching of the passivated silicon surface layer. The devices were inserted into the pits and positioned towards aligning corners and edges by specially designed tongues. The chips could be positioned with high precision on the wafer, in contrast to the fibres, due to uneven bottom surfaces of the grooves. Hence, the alignment method presented here is more suitable for chip positioning since the lateral position of the chips does not depend on the pit depth. The presented assembly systems are well suited for building hybrid microsystems, where different types of device are assembled onto a micromachined silicon substrate.

Bulk silicon holding structures for mounting of optical fibers in v-grooves

A set of micromachined structures for holding optical fibers in anisotropically etched v-grooves has been produced. The structures are made of bulk silicon and formed in the same etch step as the aligning v-grooves, using the photovoltaic electrochemical etch-stop technique (PHET). It is a selective etch method where n-type silicon etches and p-type are passivated by combining an illuminated pn-junction and an electrochemical cell using KOH as electrolyte. The structures were produced in a variety of shapes, based on cantilever beams and doubly clamped bridges. The structures substantially facilitated the mounting of the fibers into the v-grooves. Certain structures could even push the fibers down into position in the grooves.

A miniaturized single-chip silicon membrane microphone with integrated field-effect transistor

A silicon microphone with integrated field-effect transistor which is fabricated on a single chip was simulated, designed and built. The oscillating single-crystal silicon membrane is structured using the electrochemical etch-stop technique with KOH solution. It contains the channel of the transistor. The gate electrode of the transistor is made of thick polysilicon provided with ventilation holes. The membrane sidelengths vary from 500 to .

Thermally driven micromechanical bridge resonators

This paper reports the fabrication and characterization of bridge resonators made of single-crystal silicon. The fabrication process involves anisotropic etching in combination with an electrochemical etch-stop technique to obtain uniform membranes and RIE etching to free the bridges. These devices are sensitive to axial loads, and a potential application is their use as sensing elements for mechanical sensors. The drive method chosen is thermal excitation in combination with piezoresistive detection. It allows the resonating element to operate in a closed-loop electrical circuit. Several designs varying in bridge shape and resistor position have been fabricated in order to find the best parameters for a future application in a resonant sensor. Both electrical and optical measurements reveal quality factors from 200 to 400 in air. Resonant frequencies up to 1 MHz could be excited electrothermally.

PHET, an electrodeless photovoltaic electrochemical etchstop technique

A novel etchstop technique for the fabrication of micromechanical components in single-crystal silicon is presented. The photovoltaic electrochemical etchstop technique (PHET) was characterized for anisotropic etching in 7M KOH in the 60/spl deg/ to 80/spl deg/C temperature range, but can in principle be extended towards other anisotropic etchants. PHET is based on the photovoltage generated across a p/n junction illuminated during etching. In contrast with the established two-, three- or four-electrode electrochemical etchstop on n-epi, the technique does not require any external electrodes or connections to be made to the wafer, hence alleviating the need for a mechanical etchholder that protects one wafer side from the etchant. These etch-fielders are known to introduce stress and to substantially reduce yield in the production of the more fragile microstructures. Moreover, PHET is suited for the realization of diaphragm type structures in p-epi as well as for undercutting boron-diffused beam or bridge type of structures. In contrast with the established high boron dose etchstop, with its known adverse mechanical and electrical side effects, PHET does not require excessive boron concentrations. PHET therefore merges the fabrication possibilities offered by the conventional electrochemical etchstop and the conventional high boron dose etchstop, without being subject to the respective drawbacks of these techniques. The only technology required in addition to those used in the conventional etchstops is platinum sputtering. The possibilities that are offered for postprocessing standard p-well or twin-tub CMOS substrates are considered to be a major asset of the presented photovoltaic etchstop.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Etch-stop behaviour of depletion layers

The authors demonstrated that the thickness of a diaphragm using the electrochemical etch-stop technique can be monitored with the applied reverse bias voltage on individual pn-junctions. It is thus possible to produce diaphragms of differing thickness on one wafer using different reverse bias voltage values. This effect is attributed to an etch-rate reduction of approximately a factor of ten when the etch front reaches the depletion layer of the pn-junction. Since the depletion-layer thickness is voltage dependent different diaphragm thicknesses can be obtained. For a metallurgical junction depth of 4.4 mu m diaphragm thicknesses of 5.5 mu m, 6.5 mu m and 9.5 mu m were obtained for respective reverse bias values of 2 V, 8 V and 20 V. Since depletion layers can also be obtained with metal oxide silicon semiconductor (MOS) structures, MOS-capacitors with n+ source diffusions were biased with 10 V gate to substrate and 3 V source to substrate voltages. Electrochemical etching yielded membranes of typically 3 mu m thickness. They are lightly p-doped in this case (3*1015 cm-3) and completely stress free. For MOS-structures no final etch-stop can be obtained, however, etch-through monitors are used as etch end-point detectors. Very thin, single-crystal diaphragms with thicknesses below 2 mu m are of importance in several applications. Such thin diaphragms were made with shallow implanted pn-junctions of 1.2 mu m junction depth and an electrical activation anneal. The resulting diaphragm thickness obtained was 2 mu m by sufficient overetching.

Vertically structured silicon membrane by electrochemical etching

Abstract An electrochemical pn etch-stop technique is described in which the pn-junction is formed by diffusion and/or ion implantation. With more than one diffusion, a vertical membrane structure can be obtained such that the thinner membranes are suspended on thicker rims of arbitrary shape. The transition from a thick to a thin membrane has rounded contours, which are not dependent on crystal direction. An improvement of the stability of the suspension of very thin membranes is thereby achieved.

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.