Electrical Safe Operating Area Research Articles

High-voltage FinFET with floating poly and high-k material for enhanced intrinsic gain and safe operating area

We propose a new drain-extended FinFET (DeFinFET) that can improve the intrinsic gain (gm/gds) and the electrical safe operating area (SOA). This structure features a novel utilization of the drain potential by using a floating poly (FP) and split high-k material (HK) on the drain and drift regions. This method effectively controls the potential drop profile within the drift region, which makes a uniform electric field distribution in the gate-on state. The evenly distributed electric field significantly increases the on-state breakdown voltage (7.33 V) compared to a conventional structure (5.89 V). In addition, it prevents the device from operating in an undesirable quasi-saturation mode, even after space charge modulation. This operation distinguishes our results from other studies, showing a notable improvement in gm/gds. Moreover, electron accumulation is induced in the drift region, leading to a significant decrease in the on-resistance. As a result, the proposed device demonstrates clear advantages in high-voltage applications with a 45% expanded electrical SOA over conventional DeFinFET.

Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses

Electrical Safe Operating Area and Latent Damage of SiC Low-Voltage nMOS Under TLP and VF-TLP Stresses

High-k field plate DeNMOS design for enhanced performance and electrothermal SOA in switching applications

This paper investigates high-k dielectric field plate (FP) application to optimize the capacitance and avalanche behavior of conventional drain extended NMOS (C_DeNMOS) for enhanced performance and electrothermal safe operating area (SOA) in transient switching applications. Two configurations of high-k dielectric DeNMOS have been investigated: 1) Planar and 2) Trench. Doping of FP is changed from N+ to P+ in Planar, while shallow trench isolation (STI) is placed below the N+ doped FP in the Trench structure to limit surface charge accumulation in comparison to C_DeNMOS. We demonstrate that efficient reduced-surface-field (RESURF) action of high-k dielectric improves the shielding against high lateral fields, enhancing electrical and electrothermal SOA. Furthermore, for electrothermal SOA analysis, unclamped inductive switching (UIS) simulations have been performed, and it is shown that high parasitic BJT trigger voltage (Vt1) and second breakdown current (It2) enable safe turn-off of the device under high current transient conditions.

Reliability Concerns on LDMOS With Different Split-STI Layout Patterns

Compared with the full shallow trench isolation (full-STI) lateral double-diffused MOS (LDMOS), the split-STI LDMOS has been demonstrated as a superior device with better breakdown voltage (BVOFF and specific on-resistance ( ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}})$ by virtue of its low resistance current path and dielectric reduced surface field effect. The layout of STI may not only be restricted in one pattern. Instead, it can have a variety of changes based on the split-STI structure. Actually, improvement of ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}}$ can be achieved upon modifying the STI layout pattern. In this way, four STI layout patterns, named split-STI, stair-STI, slope-STI, and H-shape-STI, are proposed. However, there is lack of information about the impacts of STI layout patterns on the reliability features of LDMOS. Therefore, in this article, the reliability features of the LDMOS with different STI layout patterns are investigated in detail, including electrical safe operating area (e-SOA), electro-static discharge (ESD) robustness, and hot carrier injection (HCI) degradation. Combining the experiment and technology computer-aided design (TCAD) simulation, the root causes of different reliability features are analyzed and discussed. Comparing them each, the LDMOS with H-shape-STI is recommended because of its better reliability features.

Source Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors

In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with source-side underlap (SU), which can be integrated into any existing LDMOS/bipolar-CMOS-DMOS (BCD) process flow without any additional processing/area cost. Unlike commonly used solutions, the SU LDMOS provides flexibility to improve ON-state behavior without disturbing other performance metrics. The proposed SU LDMOS transistor is experimentally demonstrated using 180-nm CMOS technology, and noteworthy improvement in ON-state breakdown voltage, electrical safe operating area (SOA), output conductance, transistor intrinsic gain, and cutoff frequency is reported. The physics behind the improvement is also discussed in detail.

Kirk effect and suppression for 20 V planar active-gap LDMOS

For 20 V planar active-gap lateral double-diffused MOSFET (LDMOS), the sectional channel is utilized to decrease the electric field in the n-drift region below the poly gate edge in the off-state, compared with the conventional single channel. Then the n-drift concentration can be increased to decrease the Kirk effect, while keeping off-state breakdown voltage Vbd unchanged. Meanwhile the influence of the n-drift concentration and the n-drift length Ldrift (the drain n+ diffusion to gate spacing) which are related to the Kirk effect is discussed. The trade-offs between Rdson·Area, breakdown voltage Vbd and the electrical safe operating area (e-SOA) performance of LDMOS are considered also. Finally the proposed planar active-gap LDMOS devices with varied values of Ldrift are experimentally demonstrated. The experimental results show that the Kirk effect can be greatly suppressed with slight increase in the Rdson·Area parameter.

Reliability Concern on Extended E-SOA of SOI Power Devices With P-Sink Structures

The P-sink structure is widely used in silicon-on-insulator (SOI) power devices (SOI-LIGBT and SOI-LDMOS) to extend the electrical safe operating area (E-SOA) as it can suppress the trigger of the parasitic transistor. In this paper, the electrical behavior and reliability issues in the extended E-SOA for 200-V SOI power devices with P-sink structures are investigated for the first time. For SOI-LIGBT, the normal I-V curve and small hot-carrier-induced degradation are observed in the extended E-SOA; thereby, the P-sink structure plays a good role. However, for SOI-LDMOS, two mechanisms dominate the electrical behavior in the extended E-SOA so as to bring the unusual “hump” in the I- V curve; meanwhile, it results in serious hot-carrier-induced degradation, reducing the lifetime of the device in practical applications. As a result, the P-sink structure is not the best choice to extend the E-SOA of SOI-LDMOS.

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

Characteristics of lateral diffused metal–oxide–semiconductor (LDMOS) transistors with gradual junction profile by self-alignment implant through dual thicknesses of screen oxide are presented in this letter. Compared with LDMOS transistors with traditional junction profile, this new device shows improved off-state breakdown voltage, less severe in Kirk effect, and wider electrical safe operating area; without sacrificing device drivability. Technology computer aided design (TCAD) simulation results reveal that this new device has smaller electric field both in off- and on-state bias conditions. Hot-carrier induced degradation of this new device under various stress conditions is also investigated and compared with that of the device with traditional junction profile.

Analysis and optimization of lateral thin-film Silicon-on-insulator (SOI) MOSFET transistors

This paper is focused on the analysis and optimization of power N-type LDMOS (LDNMOS) transistors (VBR>120V) with the purpose of being integrated in a new generation of Smart-Power technology based upon a 0.18μm SOI-CMOS technology. The influence of some important design parameters such as the shallow trench isolation (STI) length (LSTI), the N-well doping profile and the relative position of the N-well mask to the STI block are analyzed in terms of voltage capability (VBR), specific on-state resistance (Ron-sp) and electrical safe-operating area (SOA) by means of Technology Computer-Aided Design (TCAD) numerical simulations. The evolution of the measured and simulated VBR as a function of the substrate (handle wafer) voltage (HWV) gives good physical insight of the optimal LDNMOS drift region design configuration. LDNMOS transistors with STI lengths partially covering the drift region length leads to better combined action of Ron-sp/VBR trade-off and electrical SOA results.

Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process

In high-voltage technologies, silicon-controlled rectifier (SCR) is usually embedded in output arrays to provide a robust and self-protected capability against electrostatic discharge (ESD). Although the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mistriggering of the embedded SCR during normal circuit operating conditions can bring other application reliability concerns. In particular, the safe operating area (SOA) of output arrays due to SCR insertion has been seldom evaluated. In this paper, the impact of embedding SCR to the electrical SOA (eSOA) of an n-channel LDMOS (nLDMOS) array has been investigated in a 24-V bipolar CMOS-DMOS process. Experimental results showed that the nLDMOS array suffers substantial degradation on eSOA due to embedded SCR. Design approaches, including a new proposed poly-bending (PB) layout, were proposed and verified in this paper to widen the eSOA of the nLDMOS array with embedded SCR. Both the high ESD robustness and the improved SOA of circuit operation can be achieved by the new proposed PB layout in the nLDMOS array.

Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Numerical TCAD and transmission line pulse analysis of an electrical safe operating area of a robust p-channel lateral DMOS transistor is performed. The observed independence of the trigger current on the applied gate-source voltage is attributed to a lack of quasi-saturation effect which is usually observed in an n-channel LDMOS. The dependence of the trigger voltage on the length of channel and drift regions is also analyzed, and the tradeoff with the specific on-resistance (RDSon) is given.

Enhancement of the Electrical Safe Operating Area of Integrated DMOS Transistors With Respect to High-Energy Short Duration Pulses

The influence of the source/body layout on the electrical safe operating area (SOA) of both vertical and lateral double-diffused metal-oxide-semiconductor transistors is experimentally investigated using a transmission line pulse system. Tradeoff between RDSon ·Area and SOA is discussed. Stripe geometries with and without (i.e., conventional design) body contact extension and cell designs with circular and oval geometries are considered. It is shown that a circular design of the source/body cell is superior with respect to SOA, compared with the conventional stripe design. The oval design is used to improve RDSon ·Area without compromising SOA performance, compared with the circular design.

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

The total safe operating area of both lateral and vertical integrated DMOS power transistors is evaluated. The electrical, hot carrier and thermal safe operating area of both devices types is investigated, and a comparison is made. It is found that the vertical DMOS exhibits a superior hot carrier and electrical safe operating area, mainly being due to the absence of a field oxide dot in the device drift region. The thermal safe operating area of LDMOS and VDMOS is identical.

On the electrical SOA of integrated vertical DMOS transistors

The dependency of the electrical safe operating area (SOA) of an integrated vertical DMOS transistor on the layout as well as on the residual epitaxial thickness of the drift region, is experimentally investigated using transmission line pulsing experiments. Guidelines for optimizing the SOA without compromising the other device parameters are given.

Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)

Thermal and electrical destruction of 55 V single and double reduced surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) in smart power ICs are investigated by experiments, simulations, and theoretical modeling. Static safe operating area (SOA) and single pulse dynamic SOA (energy capability) have been studied and correlated. Single RESURF device failure and hence the energy capability is controlled by electrical phenomenon for drain to source voltage near breakdown voltages, whereas the energy capability of the double RESURF device is shown to be controlled by thermal phenomenon for voltage ranges up to about 5 V below the breakdown voltage. Measured energy capability data have been used to obtain critical temperatures for device failure, which decreases with an increase in drain to source voltage. We have empirically shown using experimental data that if the dynamic SOA of the device comes within about 2-5/spl times/ of the static SOA boundary, the device failure is strongly influenced by avalanche multiplication. An analytical model based on Green's function formulation is derived and proposed which can predict energy capability of LDMOSFETs for a wide range of device geometry. The calculated data show excellent matching with the measurements and are within /spl plusmn/10%. A new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device.