Electrical Properties Of MOS Devices Research Articles

Reliability and Thermal Stability of Clustered Vertical Furnace-Grown $\hbox{SiO}_{2}$ With $\hbox{Hf}_{\rm x}\hbox{Ta}_{\rm y}\hbox{N}$ Metal Gate for Advanced MOS Device Application

Native oxides at the Si surface on the electrical properties of MOS devices are crucial problems. To study these issues, the thermal stability and electrical characteristics of MOS devices with clustered vertical furnace-grown, native oxide-free, ultrathin gate oxides and Hf xTayN metal gates were investigated. Postmetallization annealing (PMA) was carried out to study the metal-diffusion effects. Time-of-flight secondary ion mass spectroscopy analysis results show that the diffusion depths of Hf and Ta in the gate oxide are small and stay almost constant with a PMA temperature of up to 950 degC. Compared to those with conventional horizontal furnace-grown oxides, MOS devices with advanced clustered vertical furnace-grown gate oxides show excellent electrical characteristics, such as equivalent oxide thickness, hysteresis, interface trap density, stress-induced leakage current, defect generation rate, and stress-induced flat-band voltage shift. With an increase in PMA temperature, the electrical characteristics remain almost unchanged, which, in turn, achieve the excellent thermal stability and electrical reliabilities of MOS devices with clustered vertical furnace-grown gate oxides and Hf0.27Ta0.58N0.15 metal gates

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.

Temperature dependence of the electrical properties of MOS devices constructed by sol gel deposited BaTiO3 films on p-Si

The electrical properties of MOS devices with high-k insulating BaTiO3 sol gel films fabricated onto p-Si substrates, were investigated by a variety of electrical techniques. The aim was to identify the temperature dependence of the electrical properties of the MOS devices. All samples exhibit a typical MOS behaviour. The density of interface states Dit was found to decrease with decreasing temperature and lies between 1 × 1011 eV−1 cm−2 at near midgap and 3 × 1012 eV−1 cm−2 near the gap edges. The bulk-trapped charges were calculated to be between 40 and 120 nCb cm−2. The samples depicted high dielectric constants reaching values of 120. The results revealed that the sol-gel technique creates effective microelectronic devices.

The Effect of Radiation on the Electrical Properties of MOS Devices

Samples of MOS devices which were prepared by anodic oxidation method in which three electrodes used with HCl of 0.1 M. The thicknesses of SiO2 film were between 45& 80Ao . The effect of -ray on the characteristic of these devices studied through the measurements of I-V and C-V before and after irradiation. The results point to that the capacitance decreased after irradiation and an increase in the conductivity observed which indicates a decrease of potential barriers of these devices. The measurement of I-V for these samples as solar cell showed a decrease in the output power.

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si/sub 3/N/sub 4/ and Ta/sub 2/O/sub 5/ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si/sub 3/N/sub 4/ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta/sub 2/O/sub 5/ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta/sub 2/O/sub 5/ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta/sub 2/O/sub 5/ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation.

Tuning of the electroluminescence from Si nanocrystals through the control of their structural properties

ABSTRACTWe have studied the structural, optical and electrical properties of MOS devices, where the dielectric layer consists of a substoichiometric SiOx (x < 2) thin film deposited by plasma enhanced chemical vapor deposition. After deposition the SiOx samples were annealed at high temperature (> 1000°C) to induce the separation of the Si and SiO2 phases with the formation of Si nanocrystals embedded in the insulating matrix. The effects of the Si concentration in the SiOx layer and of the annealing temperature on the electrical and optical properties of these devices are reported and discussed. It is shown that by increasing the Si content in the SiOx layers the operating voltage of the device decreases and the total efficiency of emission increases. In fact, devices having an active layer with high Si concentration (46 at.%) annealed at 1100 °C, exhibit the best performances (i.e. the highest electroluminescence intensity and the lowest operating voltage). Furthermore, we have observed that by decreasing the thickness of the SiOx layer from 75 to 25 nm it is possible to strongly reduce the operating voltage down to 4 V.

A Dual-Function Uhv-Compatible Chamber for i) Low-Temperature Plasma-Assisted Oxidation, and ii) High-Temperature Rapid Thermal Processing of Si-Based Dielectric Gate Heterostructures

ABSTRACTA combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

A Dual-Function UHV-Compatible Chamber for i) Low-Temperature Plasma-Assisted Oxidation, and ii) High-Temperature Rapid Thermal Processing of Si-Based Dielectric Gate Heterostructures

ABSTRACTA combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

Effect of rapid thermal reoxidation on the electrical properties of rapid thermally nitrided thin-gate oxides

The authors report a systematic study of the impact of post-nitridation rapid thermal anneals in oxygen and nitrogen on the electrical properties of MOS devices with thin gate oxides. A comparative study of the two annealing ambients has led to the formulation of qualitative models to describe the charge trapping properties of the respective gate dielectrics. Roles of the post-nitridation anneals in altering the radiation and hot-electron sensitivity of the MOS devices are investigated and explained on the basis of structural changes in the gate oxides during nitridation and subsequent annealing. The performance and reliability of MOSFETs with reoxidized nitrided gate oxides are investigated. Overall, the results indicate that reoxidized nitrided oxides show improved charge trapping properties, better resistance to radiation and hot-carrier stress, and improved high-field electron mobility in MOSFETs. >

Interface characterization of InSb MOS structures

The electrical properties of MOS devices are critically dependent on the oxide-semiconductor interface. The preparation of suitable insulating layers of oxide or other material is essential for the performance of such devices and it is particularly difficult in the case of III-V compound semiconductors. We report a method of preparing an insulating layer on InSb by a plasma oxidation process. The oxidation method will be described as well as results of the analysis of the oxide-semiconductor interface by electrical and compositional techniques. Capacitance-voltage characteristics reveal the existence of interface states which are distributed near the conduction and the valence bands with a higher density near the former. Depth profiling of the oxide by Ar + sputtering and Auger electron spectroscopy (AES) shows that the oxide is composed of a mixture of indium oxide with the antimony oxide. At the interface a transition region can clearly be observed, whose composition seems to be mostly indium oxide rich in metallic antimony. This information can be derived from the Auger line shapes and positions. We find AES to be an extremely helpful tool for this kind of investigation, in spite of the obvious disadvantages of ion sputtering, especially in the case of indium and antimony. Correlations of the AES data with the electrical analysis results are suggested.

Selective Plasma Oxidation of GaAs –A Study of the Interface Properties

Studies by electron and photon spectroscopy show that plasma grown GaAs oxide possesses an excess amount elemental As at the oxide–GaAs interface. This amount has been found to be inversely proportional to the growth rate. The excess elemental As is deleterious to the electrical properties of MOS devices. A selective plasma oxidation process using fluorinated oxygen gas shows that the excess As at the interface can be greatly reduced. The resultant electrical properties are also improved.