Electrical Properties Of GaAs Research Articles

III-V Thin-Film Solar Cells Bonded to Si Substrates via Metal Grids

Ⅲ-Ⅴ on Si multijunction (MJ) solar cells are promising as next-generation solar cells since they can provide high efficiency with low cost in comparison with conventional Si and Ⅲ-Ⅴ MJ cells. In fabricating such III-V/Si MJ cells, Ⅲ-Ⅴ subcells are placed on Si bottom cell by hybrid approaches such as surface-activated bonding (SAB). The bonding interfaces with lower interface resistances are strongly required so as to achieve better performance of hybrid MJ cells.It was found that the resistance across the directly-bonded III-V/Si interfaces in MJ cells was higher than the resistance in junctions made of heavily-doped substrates because of the thin heavily-doped bonding layers in actual subcell structures. It was reported that indium tin oxide (ITO) films as intermediate layers between III-V and Si subcells played a role of lowering the series resistance of MJs [1]. It was found, however, that the resistance of GaAs//ITO/Si junctions increased by annealing them [2]. Furthermore, the quantum efficiency of Si bottom cells was lowered by inserting the ITO layers because of the free carrier absorption of ITO layers.These problems are assumed to be avoided by using metal grids in combination with dielectric materials such as SiO2 and SiN. Figure 1(a) shows a schematic process for fabricating Ⅲ-Ⅴ/metal grid/Si MJ cells. Metal grid structures work as ohmic contacts for both of Ⅲ-Ⅴ and Si layers. Dielectric materials, such as SiO2 and SiN, are likely to work as passivation for Si subcells. The metal grids must be slightly thicker than the dielectric materials so as to ensure successful bonding of semiconductor to metal grid. It is also notable that impacts of shadow loss due to the metal grid can be minimized by aligning the emitter contacts on the top cells to the metal grids. We recently fabricated Si//metal grid/Si and GaAs//metal grid/Si junctions by SAB and reported on their electrical characteristics [3]. In this work, we fabricate III-V cells bonded on conductive Si substrates via metal grids and examine their photovoltaic properties.We prepared n-on-p InGaP/GaAs double-junction (2J) epi layers grown on GaAs substrates. The epi substrates were bonded to p-Si substrates via metal grids using SAB. 2J cells were fabricated by removing the GaAs substrates and forming emitter and base contacts on the top and bottom surfaces, respectively. The top view of the fabricated cells is shown in Fig. 1(b). Note that the emitter contacts were aligned to metal grids. Their current-voltage (I-V) characteristics under the solar irradiance of AM1.5G/one sun, which were obtained by using an in-house solar simulator, are shown in Fig. 1(c). The observed open-circuit voltage and short-circuit current (2.47 V and 10.9 mA/cm2) indicate that the fabricated cells normally work as 2J cells. Although the structure and fabrication process are not yet optimized, the results that we obtained suggests that the bonding via metal grids are promising for fabricating hybrid MJ cells with low series resistance.[1] Naoteru Shigekawa, Tomoya Hara, Tomoki Ogawa, Jianbo Liang, Takefumi Kamioka, Kenji Araki, and Masafumi Yamaguchi, "GaAs/Indium Tin Oxide/Si Bonding Junctions for III-V-on-Si Hybrid Multijunction Cells With Low Series Resistance", IEEE J. Photovolt. 8 (3), pp. 879-886 (2018).[2] Tomoya Hara, Tomoki Ogawa, Jianbo Liang, Kenji Araki, Takefumi Kamioka, and Naoteru Shigekawa, "Electrical properties of GaAs//indium tin oxide/Si junctions for III-V-on-Si hybrid multijunction cells", Jpn. J. Appl. Phys. 57, 08RD05 (2018).[3]Takashi Hishida, Jianbo Liang, and Naoteru Shigekawa, "Low-resistance semiconductor/semiconductor junctions with intermediate metal grids for III-V-on-Si multijunction solar cells", Jpn. J. Appl. Phys. 59, SB, SBBB04 (2020). Figure 1

Effects of La content in ZrLaON gate dielectric on the interfacial and electrical properties of GaAs metal-oxide-semiconductor devices

GaAs MOS capacitors with ZrLaON as the high-k dielectric layer and LaON as the interfacial passivation layer (IPL) are fabricated and the effects of the La content in ZrLaON on the device performance are investigated. Experimental results show that ZrLaON with a moderate or high La content induces serious moisture absorption, thus deteriorating the interfacial and electrical properties of the device, even with the LaON IPL. By adjusting the La content to a suitable value, e.g. a La/(La + Zr) atomic ratio of 13%, good interfacial and electrical properties can be obtained because the passivating role of La on the defects in ZrON can over-compensate the performance degradation induced by the moisture absorption. With the LaON IPL, further improvements in interfacial and electrical properties can be achieved because the LaON IPL can effectively passivate the As-O, Ga-O and As-As bonds at/near the high-k/GaAs interface.

Electrical properties of GaAs//indium tin oxide/Si junctions for III–V-on-Si hybrid multijunction cells

The electrical properties of GaAs//indium tin oxide (ITO)/Si junctions fabricated by surface-activated bonding (SAB) are investigated with emphasis on their dependence on the temperature of postbonding annealing. The current–voltage (I–V) characteristics of n+-GaAs//ITO/p+-Si and n+-GaAs//ITO/n+-Si junctions without annealing are linear. Those of p+-GaAs//ITO/p+-Si and p+-GaAs//ITO/n+-Si junctions without annealing are nonlinear. Although the interface resistance of all the junctions increases with increasing annealing temperature, the resistances of the respective junctions after the annealing at 400 °C are still smaller than the series resistance of the actual SAB-based InGaP/GaAs//Si hybrid triple-junction cells (∼4 Ω cm2). The n+-GaAs//ITO/n+-Si junction reveals the lowest resistance among the investigated junctions after annealing. These results demonstrate that GaAs//ITO/Si junctions with an ITO intermediate layer could be effective for reducing series resistance in hybrid multijunction cells.

Interfacial and Electrical Properties of GaAs Metal-Oxide-Semiconductor Capacitor with ZrAlON as the Interfacial Passivation Layer**Supported by the National Natural Science Foundation of China under Grant Nos 61176100, 61274112 and 61404055.

The ZrTiON gate-dielectric GaAs metal-oxide-semiconductor (MOS) capacitors with or without ZrAlON as the interfacial passivation layer (IPL) are fabricated and their properties are investigated. The experimental results show that the GaAs MOS capacitor with the ZrAlON IPL exhibits better interfacial and electrical properties, including lower interface-state density ( cm−2eV−1), smaller gate leakage current ( A/cm2 at +1 V), smaller capacitance equivalent thickness (1.5 nm), and larger k value (26). The involved mechanisms lie in the fact that the ZrAlON IPL can effectively block the diffusion of Ti and O towards the GaAs surface, thus suppressing the formation of interfacial Ga-/As-oxides and As-As dimers, which leads to improved interfacial and electrical properties for the devices.

Review Article: Molecular beam epitaxy of lattice-matched InAlAs and InGaAs layers on InP (111)A, (111)B, and (110)

For more than 50 years, research into III–V compound semiconductors has focused almost exclusively on materials grown on (001)-oriented substrates. In part, this is due to the relative ease with which III–Vs can be grown on (001) surfaces. However, in recent years, a number of key technologies have emerged that could be realized, or vastly improved, by the ability to also grow high-quality III–Vs on (111)- or (110)-oriented substrates These applications include: next-generation field-effect transistors, novel quantum dots, entangled photon emitters, spintronics, topological insulators, and transition metal dichalcogenides. The first purpose of this paper is to present a comprehensive review of the literature concerning growth by molecular beam epitaxy (MBE) of III–Vs on (111) and (110) substrates. The second is to describe our recent experimental findings on the growth, morphology, electrical, and optical properties of layers grown on non-(001) InP wafers. Taking InP(111)A, InP(111)B, and InP(110) substrates in turn, the authors systematically discuss growth of both In0.52Al0.48As and In0.53Ga0.47As on these surfaces. For each material system, the authors identify the main challenges for growth, and the key growth parameter–property relationships, trends, and interdependencies. The authors conclude with a section summarizing the MBE conditions needed to optimize the structural, optical and electrical properties of GaAs, InAlAs and InGaAs grown with (111) and (110) orientations. In most cases, the MBE growth parameters the authors recommend will enable the reader to grow high-quality material on these increasingly important non-(001) surfaces, paving the way for exciting technological advances.

Improved interfacial quality of GaAs metal-oxide-semiconductor device with NH3-plasma treated yittrium-oxynitride as interfacial passivation layer

The interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with yittrium-oxynitride interfacial passivation layer treated by N2−/NH3-plasma are investigated, showing that lower interface-state density (1.24×1012cm−2eV−1 near midgap), smaller gate leakage current density (1.34×10−5A/cm2 at Vfb+1V), smaller capacitance equivalent thickness (1.43nm), and larger equivalent dielectric constant (24.5) can be achieved for the sample with NH3-plasma treatment than the samples with N2−/no-plasma treatment. The mechanisms lie in the fact that NH3-plasma can provide not only N atoms, but H atoms and NH radicals to effectively passivate the high-k/GaAs interface, thus less pinning the Femi level at high-k/GaAs interface.

Electrical Properties OF GaAs Doped with Iron

Gallium arsenide doped with iron is used for manufacturing photodetectors and avalanche S- diodes. It is also a promising material for spintronic devices [1, 2]. Doping of gallium arsenide with iron can be carried out in several ways: in the processes of growth of single crystals [3], diffusion, ion implantation, vapor phase and molecular beam epitaxy [1]. Magnetic properties of GaAs: Fe are studied intensively beginning with the works [4, 5]. The data on the electrical properties of GaAs doped with iron and the position of the energy level of Fe in GaAs are systematized in the review [6]. Mainly, GaAs:Fe doped during the growth of single crystals by Czochralski technique was investigated. According to different authors, an acceptor level of Fe occupies different positions in the GaAs bandgap. The most reliable result, according to the authors [6], is the level

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm−2 eV−1), small gate leakage current (7.3 × 10−5 A cm−2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Electrical properties of GaAs metal-oxide-semiconductor structures with the oxide layer grown by liquid phase chemical-enhanced method

The oxide films prepared by liquid phase chemical-enhanced technique were electrically characterized using current–voltage and capacitance–voltage measurements on metal-oxide-semiconductor (MOS) structure. It was found that the leakage current density is roughly (1–2)×10 −6 A cm −2 at the electric filed of 1 MV cm −1. The oxides with denser structures exhibit higher refractive indices, higher reliability and also higher breakdown voltages. The breakdown fields of ∼7 MV cm −1 were obtained as refractive index is ∼2.12. In addition, dielectric constant of oxide films is found to increase with increasing thickness and varies within a wide range from 3.2 to 11 under accumulation region. Furthermore, short time ramp-voltage, constant-voltage and constant-current stress are employed to reliability study.

PH 3 /H 2 plasma passivation of metal-organic chemical vapor deposition grown GaAs on Si

Effects of PH3/H2 (PH3/H2=10%) plasma passivation of GaAs grown on Si substrate have been investigated in detail. It is observed that both the surface phosphidization and defect hydrogenation can be realized simultaneously with a reduced plasma-induced damage. The optical and electrical properties of GaAs on Si are effectively improved by PH3/H2 plasma exposure due to the passivation of bulk and surface defects-related nonradiative recombination centers by incorporation of hydrogen (H) and phosphorous (P) atoms. As a result, the PH3/H2 plasma exposed GaAs Schottky diodes on Si show an increase in the reverse breakdown voltage by a factor of about 1.6, and the as-passivated GaAs solar cell grown on Si shows an increase in the conversion efficiency from 15.9% to 18.6% compared to that of the as-grown samples. The passivated GaAs devices on Si show outstanding thermal stability, which is probably due to the active participation of both H and P atoms in the PH3/H2 plasma passivation process.

A comparative study of carbon incorporation in heavily doped GaAs and Al0.3Ga0.7As grown by solid-source molecular beam epitaxy using carbon tetrabromide

The electrical properties of carbon doped GaAs and AlGaAs were studied as a function of substrate temperature and CBr4 flux for the doping range ∼1018–1020 cm−3. Hall measurements indicate a strong reduction in the free carrier concentration of GaAs films grown with the same CBr4 flux at substrate temperatures above 620 °C. Secondary ion mass spectroscopy measurements, however, show no reduction of chemical carbon concentration. The electrical properties of GaAs:C epilayers grown on (n11)A and B surfaces, where n=2–5, show strong dependence on crystallographic orientation. Based on these measurements, the model of free carrier concentration reduction in GaAs:C based on formation of electrically inactive C–C pairs has been proposed. In contrast, no anomalous carbon incorporation in AlGaAs has been detected for the doping range ∼1018–1020 cm−3 and the substrate temperature range 550–700 °C. The resulting material exhibits excellent transport and optical properties.

Amorphous GaAs1 − xNx thin films on crystalline Si substrates: growth and characterizations

Abstract This work deals with the growth and study of a new nitride in thin films: GaAs 1 − x N x . The material is deposited in its amorphous form on crystalline Si substrates by means of RF sputtering of a GaAs target in an atmosphere of argon and ammonia. Raman spectroscopy used to study the physico-chemical properties of the film structure pointed out that GaAs 1 − x N x is a wide gap material which is formed by the substitution of arsenic by nitrogen in the GaAs network (J. Bandet, K. Aguir, D. Lollman, A. Fennouh, H. Carchano, Jpn. J. Appl. Phys., 36 (1997) 11. In order to investigate the electrical properties of GaAs 1 − x N x in view of potential applications in optoelectronic systems, J—V and C—V characteristics have been performed. J—V results show that the heterostructures exhibit a drastic increase in resistivity with nitrogen incorporation. The conduction passes from a diode-type one for x = 0 to an approximately symmetrical one with nitridation, i.e. for x > 0. The films present convenient high resistivity values for insulating character consideration. Furthermore, C—V results obtained present a manifest MIS-like behaviour with however the existence of a flat-band voltage ( V FB ).

The influence of ion energy, ion flux, and etch temperature on the electrical and material quality of GaAs etched with an electron cyclotron resonance source

The residual damage incurred to GaAs via etching with a Cl2/Ar plasma generated by an electron cyclotron resonance (ECR) source was investigated as a function of variations in ion energy, ion flux, and etching temperature. The residual damage and electrical properties of GaAs were strongly influenced by changes in these etching parameters. Lattice damage was incurred in all processing situations in the form of small dislocation loops. GaAs etched at high ion energies with 200 W rf power, exhibited a defect density five times higher than GaAs etched at lower ion energies with 20 W rf power. This enhanced residual damage at the higher rf powers was paralleled by a degradation in the unannealed contact resistance. Higher etch rates, which accompany the higher rf power levels, caused the width of the disordered region to contract as the rf power was elevated. Therefore, the residual etch damage is influenced by both the generation and removal of defects. Increasing the microwave power or ion flux resulted in elevating the residual defect density, surface roughness, and unannealed contact resistance. GaAs etched at high temperatures, ∼350 °C, resulted in a lower contact resistance than GaAs etched at 25 °C. The high temperature etching augmented the defect diffusion which in turn lowered the near surface defect density. This decrease in residual damage was deemed responsible for improving the electrical performance at 350 °C. The electrical measurements were found to be more sensitive to the density of defects than the vertical extent of disorder beneath the etched surface. Results of this investigation demonstrate that in order to minimize material damage and improve electrical performance, etching with an ECR source should be performed at low rf and microwave powers with a high substrate temperature.

The electrical properties of sulfur-passivated and rapidly thermally annealed GaAs metal-oxide-semiconductor structures with the oxide layer grown anodically

The effects of rapid thermal annealing (RTA) and sulfur passivation of GaAs on the electrical properties of GaAs metal-oxide-semiconductor (MOS) structures were investigated. The oxide layers were grown by anodization. Annealing was performed after oxidation and before aluminum evaporation. Passivation improved the electrical properties. Further improvements were obtained after RTA. The MOS structures on passivated GaAs showed good thermal stability compared with those on unpassivated GaAs. The bond model and possible modifications in the structure of the oxide were used to explain the observations.

Effects of Heat Treatment on the Structural Defects and Electrical Properties of GaAs.

Effects of Heat Treatment on the Structural Defects and Electrical Properties of GaAs.

The role of microstructure in the electrical properties of GaAs grown at low temperature

We have examined the role of As precipitates on transport through undoped GaAs grown at low temperature by molecular beam epitaxy and annealed at high temperature. Temperature dependent I–V measurements exhibit two regimes. At temperatures less than ∼200K, transport attributed to point defect-associated hopping conduction is observed even for samples annealed at 750°C. For temperatures greater than ∼200K, the transport is quantitatively consistent with calculations of thermally assisted tunneling emission of electrons from metallic As precipitates acting as buried Schottky barriers.

Optical characterization of the electrical properties of processed GaAs

Optical spectroscopies such as photoreflectance offer unique and non-invasive tools that can be used to probe the bulk and surface electrical properties of processed semiconductors. Because of their contactless nature, they can also serve as in-situ, as well as ex-situ diagnostics of processing effects during various stages of optoelectronic device formation. In this paper, we will focus on the applications of photoreflectance to study the effects of various processing procedures such as dry etching, surface passivation and metallization on the electrical properties of GaAs. We will show how certain information, such as barrier heights and densities of surface states can be obtained in a contactless fashion.

Influence of the implantation of C+ ions on photoluminescence and electrical properties of GaAs

Ion implantation of carbon (C) into extremely pure GaAs grown by molecular- beam epitaxy is carried out over a wide range of C atomic concentrations [C], from 1×1016 to 5×1019 cm−3. The impurity levels in the implanted layer are investigated by using photoluminescence (PL) and Hall-effect measurements. Below the well-defined exciton luminescence lines, one broad emission band, namely [g-g], is found to be exclusively attributable to acceptor impurities and is dominant for [C] lower than 3×1017 cm−3. However, a decrease of its intensity and a ‘‘locking’’ of its emission energy shift is observed for [C] higher than this value. A carrier transport mechanism is found to be relevant to the C acceptor level for C atoms at As sites, and deep acceptors caused by residual radiation defects. The concentration of substitutional C atoms is nearly coincident with [C] up to 1×1017 cm−3, but the activation efficiency for [C]=1×1018 cm−3 decreases by about 13%. The decrease of overall PL intensity and the locking of the emission energy shift of [g-g] are the peculiar features in highly C+- implanted GaAs. Moreover, the location of a moderately deep acceptor level and its related-emission properties as a function of [C] strongly suggest the formation of complexes involving arsenic vacancies (VAs) and C impurities, or residual radiation defects.

Electrical Properties of Mesa Diodes on Epitaxial GaAs/Si

AbstractDeep level transient spectroscopy (DLTS), current-voltage- temperature (I-V-T), capacitance-voltage-temperature (C-V-T), C-T and photoreflectance spectroscopy (PRS) were used to compare the electrical properties of GaAs p-n junctions epitaxially grown by MOCVD on GaAs and Si substrates. EL2 was detected for both GaAs/GaAs and GaAs/Si structures. For GaAs/Si, a continuous distribution of trap levels was also observed which could be ascribed to misfit defects. I-V-T data revealed the saturation current of GaAs/Si diodes to be four orders in amplitude higher than for GaAs/GaAs ones. Different temperature dependences were found in saturation current density, barrier height and capacitance between the two structures. A multistep tunneling model is utilized in explaining the results for GaAs/Si. C-T measurements indicated the free carriers not to be frozen-out for GaAs/Si at the freeze-out temperature of GaAs/GaAs. A defect- induced bandgap tailing effect might be responsible for this effect, verified by PRS tests.

Effect of a coincident Pb flux during mbe growth on the electrical properties of GaAs and AlGaAs layers

The effect of a coincident Pb flux during molecular beam epitaxial growth on the electrical properties of undoped GaAs and Si doped Al x Ga 1− x As layers is investigated. In undoped GaAs, the concentration of electron trap is decreased with the Pb flux. In the case of Si doped Al x Ga 1− x As, the Pb flux is shown to reduce the incorporation rate constant of Si. From the carrier concentration profile, the incorporation rate constant of Si for AiGaAs both with and without Pb flux are determined for the first time.