Electrical Characteristics Of Junctions Research Articles

Electrical effect of CdSe layer thickness deposited on p- Si wafer

In this paper, the current-voltage characteristics of n-CdSe/p-Si heterostructures are analyzed using experimental data and electrical junction characteristics. To develop n-CdSe/p-Si heterojunctions, a wide band gap semiconducting layer of n-type CdSe thin film has been grown on a p-type Si (100) substrate at 100oC with different thickness by using the spray pyrolysis technique. The I-V characteristic of n-CdSe\ p-Si heterostructure has been measured in a room in the dark and under illumination (lamp/160 W). Also, the solar cell IV characteristics and efficiency were measured. The characteristic parameters of the structure such as barrier height, ideality factor, and series resistance were determined from the current-voltage measurement.

Planar micro- and nano-patterning of GaN light-emitting diodes: Guidelines and limitations

The emission area of GaN light-emitting diodes can be patterned by etch-free current aperturing methods which exploit the thin and highly resistive nature of the p-doped layer in these devices. Here, the fundamental underlying electrical and optical aspects of high-resolution current aperturing are investigated theoretically. The most critical parameter for the possible resolution is the thickness d of the p-GaN layer, but the interplay of p-GaN resistivity and electrical junction characteristics is also important. A spatial resolution of 1.59d can in principle be achieved, corresponding to about 300 nm in typical epitaxial structures. Furthermore, the emission from such a small emitter will spread by about 600 nm while propagating through the p-GaN. Both values can be reduced by reducing d.

Characteristics of junctions and resistors fabricated using an all-NbN superconductor integrated circuit foundry process

Trilayer NbN/MgO/NbN tunnel junctions and Mo and NbN/sub x/ resistors fabricated over a NbN ground plane form the basis of a high performance, 10 K, superconductor integrated circuit foundry process. To produce high yield LSI and VLSI superconductor integrated circuits requires predictable device characteristics, stable, well-characterized, thin film deposition processes, and control of critical dimensions (CD). In this paper, we discuss improvements in thin film deposition processes, device characteristics, and CD control. Repeatable trilayer characteristics have been achieved through the use of feedback control of critical MgO and NbN sputtering parameters. Run-to-run variations in MgO film thickness have been reduced to less than /spl plusmn/1.0% (1/spl sigma/) using a novel computer feedback control technique. Improvements in MgO deposition uniformity and CD control of junction size have reduced across wafer I/sub c/ nonuniformity to less than /spl plusmn/10% (3/spl sigma/) and 100 junction array I/sub c/ nonuniformity on 0.5 cm chips to /spl plusmn/2% (1/spl sigma/). We report on the electrical characteristics of junctions and resistors and on component spreads and stability of our NbN foundry process.

Theoretical and experimental responsivity of fir antenna coupled metal-insulator-metal detectors

In this work we report a complete theory of the metal-insulator-metal, antenna coupled, mm and sub-mm detectors. The voltage -power responsivity is simply derived from the geometrical antenna proprieties and the electrical junction characteristics. The calculated responsivity simply foresees our experimental results in the sub-mm — mm range and well fits all the previously reported data

Fabrication and dc characteristics of small-area tantalum and niobium superconducting tunnel junctions

We discuss the fabrication and dc electrical characteristics of small-area (1–6 μm2) superconducting tunnel junctions with Ta or Nb base electrodes and Pb or Pb0.9Bi0.1 counterelectrodes. These junctions have very small subgap leakage currents, a ‘‘sharp’’ current rise at the sum-gap voltage, and show strong quantum effects when used as microwave mixers. The use of a low-energy (∼150 eV) ion cleaning process and a novel step-defined fabrication process that eliminates photoresist processing after base electrode deposition are discussed. Tunnel barriers formed by dc glow discharge oxidation were the most successful. Tunnel barrier formation by thermal oxidation and ion-beam oxidation is also discussed. An oxidized Ta overlayer (∼7 nm thick) was found to improve the characteristics of Nb-based junctions. The electrical characteristics of junctions with different electrode and barrier materials are presented and discussed in terms of the physical mechanisms that lead to excess subgap current and to a width of the current rise at the sum-gap voltage.

Activation and diffusion during rapid thermal annealing of arsenic and boron implanted silicon

The redistribution of arsenic and boron implanted respectively in single crystal and in preamorphized silicon wafers is investigated after rapid thermal annealing (RTA) at temperatures ranging from 1000 up to 1150°C. SIMS dopant profiles are compared to calculated distributions for which the diffusion equation is solved with a diffusivity depending on temperature, on impurity concentration and, eventually, on time. For both ions, an additional diffusion has to be considered. This excess diffusivity is shown to be dependent on RTA duration. Using channeling-backscattering measurements, this behaviour is clearly related to the coarsening or to the annealing of residual extended defects. Thus, the enhanced diffusion is explained by an excess point defects surviving SPE regrowth, which can be trapped or released on dislocation arrays. The electrical characteristics of junctions prepared by implantation and RTA are presented.

Electrical Properties of Vapor-Grown Ge Junctions

A method of fabricating p-n junctions and p-n junction devices by a closed-cycle iodide vapor-growth process is described. The electrical characteristics of junctions made by alternately depositing p-type and n-type germanium onto a germanium substrate compare favorably with those fabricated by other means. Device arrays, such as diode matrices, and multijunction structures have been made by this process. If sufficient control can be achieved, devices having a wide range of impurity distributions and geometric configurations will be possible.