Electric Double Layer Gate Research Articles

Impact of Large Gate Voltages and Ultrathin Polymer Electrolytes on Carrier Density in Electric-Double-Layer-Gated Two-Dimensional Crystal Transistors.

Electric-double-layer (EDL) gating can induce large capacitance densities (∼1-10 μF cm-2) in two-dimensional (2D) semiconductors; however, several properties of the electrolyte limit performance. One property is the electrochemical activity which limits the gate voltage (VG) that can be applied and therefore the maximum extent to which carriers can be modulated. A second property is electrolyte thickness, which sets the response speed of the EDL gate and therefore the time scale over which the channel can be doped. Typical thicknesses are on the order of micrometers, but thinner electrolytes (nanometers) are needed for very-large-scale-integration (VLSI) in terms of both physical thickness and the speed that accompanies scaling. In this study, finite element modeling of an EDL-gated field-effect transistor (FET) is used to self-consistently couple ion transport in the electrolyte to carrier transport in the semiconductor, in which density of states, and therefore quantum capacitance, is included. The model reveals that 50 to 65% of the applied potential drops across the semiconductor, leaving 35 to 50% to drop across the two EDLs. Accounting for the potential drop in the channel suggests that higher carrier densities can be achieved at larger applied VG without concern for inducing electrochemical reactions. This insight is tested experimentally via Hall measurements of graphene FETs for which VG is extended from ±3 to ±6 V. Doubling the gate voltage increases the sheet carrier density by an additional 2.3 × 1013 cm-2 for electrons and 1.4 × 1013 cm-2 for holes without inducing electrochemistry. To address the need for thickness scaling, the thickness of the solid polymer electrolyte, poly(ethylene oxide) (PEO):CsClO4, is decreased from 1 μm to 10 nm and used to EDL gate graphene FETs. Sheet carrier density measurements on graphene Hall bars prove that the carrier densities remain constant throughout the measured thickness range (10 nm-1 μm). The results indicate promise for overcoming the physical and electrical limitations to VLSI while taking advantage of the ultrahigh carrier densities induced by EDL gating.

Enhancing photoresponse by synergy of electric double layer gate and illumination in single CuTCNQ NW field effect transistors

<p class="BodyText1"><span lang="EN-IN">We report that photoresponse of </span><span lang="EN-US">a single metal-organic charge transfer complex Cu:TCNQ nanowire (NW)</span><span lang="EN-IN"> can be enhanced simultaneously by illumination as well as applying a gate bias in an Electric Double Layer Field Effect Transistor (EDL-FET) configuration fabricated on </span><span lang="EN-US">Cu:TCNQ </span><span lang="EN-IN">as a channel.</span><span lang="EN-IN">It is observed that applying a bias using an EDL gate to a n-channel Cu:TCNQ single NW FET, one can enhance the photoresponse of the Cu:TCNQ substantially over that which arise from the photoconductive response alone. </span><span lang="EN-US">Electron-hole pairs that generate in the NW under illuminated of wavelength 400nm gives rise photo current. Also, electric double layer induce negative charges in the NW channel which effectively increases the carrier concentration, contributing to better response in conduction. </span><span lang="EN-IN">The effect reported here has a generic nature that gives rise to a class of gated photodetectors of different photoresponsive materials.</span></p>

Effect of gate bias sweep rate on the threshold voltage of in-plane gate nanowire transistor

In2O3 nanowire electric-double-layer (EDL) transistors with in-plane gate gated by SiO2 solid-electrolyte are fabricated on transparent glass substrates. The gate voltage sweep rates can effectively modulate the threshold voltage (Vth) of nanowire device. Both depletion mode and enhancement mode are realized, and the Vth shift of the nanowire transistors is estimated to be 0.73V (without light). This phenomenon is due to increased adsorption of oxygen on the nanowire surface by the slower gate voltage sweep rates. Adsorbed oxygens capture electrons and cause a surface of nanowire channel was depleted. The operation voltage of transistor was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance. These transparent in-plane gate nanowire transistors are promising for “see-through” nanoscale sensors.

Controlling the threshold voltage of SnO2 nanowire transistors with dual in-plane-gate structures gated by chitosan proton conductors

We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to −1.0 V, we tuned the threshold voltage of these transistors from −0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

High performance thin film transistor (flex-TFT) with textured nanostructure ZnO film channel fabricated by exploiting electric double layer gate insulator

We report a flexible thin film transistor (flex-TFT) fabricated on a commonly available polyimide (Kapton®) tape with a channel of highly textured nanocrystalline ZnO film grown by pulsed laser deposition. The flex-TFT with an electric double layer (EDL) gate insulator shows a low threshold for operation (Vth ≤ 1 V), an ON/OFF ratio reaching ≈107 and a subthreshold swing ≈75 mV/dec. The superior performance is enabled by a high saturation mobility (μs ≈ 70 cm2/V s) of the highly textured nanocrystalline channel. The low Vth arises from large charge density (≈1014/cm2) induced into the channel by EDL gate insulator. The large charge density induced by the EDL gate dielectric also enhances the Hall mobility in the film and brings down the sheet resistance by nearly 2 orders, which leads to large ON/OFF ratio. The flex-TFT operation can be sustained with reproducibility when the TFT is bent down to a radius of curvature ≈2 cm.

Few-layer HfS2 transistors.

HfS2 is the novel transition metal dichalcogenide, which has not been experimentally investigated as the material for electron devices. As per the theoretical calculations, HfS2 has the potential for well-balanced mobility (1,800 cm2/V·s) and bandgap (1.2 eV) and hence it can be a good candidate for realizing low-power devices. In this paper, the fundamental properties of few-layer HfS2 flakes were experimentally evaluated. Micromechanical exfoliation using scotch tape extracted atomically thin HfS2 flakes with varying colour contrasts associated with the number of layers and resonant Raman peaks. We demonstrated the I-V characteristics of the back-gated few-layer (3.8 nm) HfS2 transistor with the robust current saturation. The on/off ratio was more than 104 and the maximum drain current of 0.2 μA/μm was observed. Moreover, using the electric double-layer gate structure with LiClO4:PEO electrolyte, the drain current of the HfS2 transistor significantly increased to 0.75 mA/μm and the mobility was estimated to be 45 cm2/V·s at least. This improved current seemed to indicate superior intrinsic properties of HfS2. These results provides the basic information for the experimental researches of electron devices based on HfS2.

Double-gate SnO2 nanowire electric-double-layer transistors with tunable threshold voltage

Double-gate Sb-SnO2 nanowire electric-double-layer (EDL) transistors with in-plane gates were fabricated using only one shadow mask. The threshold voltage of such devices can be tuned in a wide range from −0.13 V to 0.72 V by the in-plane gate, which allows the device to switch from depletion-mode to enhancement-mode operation. The operation voltage of the double-gate device is 1 V because the EDL gate dielectric can lead to a high gate capacitance (>3.5 μF/cm2). Moreover, all double-gate devices show good electrical characteristics with high field-effect mobility (>200 cm2/V·s), high drain-current Ion/off ratio (>7 × 104), and small subthreshold slope (<100 mV/dec). These double-gate nanowire EDL transistors can pave the way for an electrically working low-voltage nano-electronic process.

Ultralow-Voltage Electric-Double-Layer Oxide-Based Thin-Film Transistors with Faster Switching Response on Flexible Substrates

Phosphosilicate glass (PSG) electrolyte films are deposited by improving the content of phosphorus doping during plasma-enhanced chemical vapor deposition, and a fast electric-double-layer (EDL) polarization response of 100 kHz is measured. The mechanism of the fast polarization response and EDL formation are investigated in detail. By using PSG electrolyte films as gate dielectrics, indium-zinc-oxide (IZO) thin-film transistors (TFTs) are fabricated on flexible plastic substrates. Due to the huge EDL gate capacitance, such TFTs show only 0.8 V operation and excellent electrical performances with a large current on/off ratio of 107, low subthreshold swing of 72 mV/decade and high field-effect mobility of 16.76 cm2/V·s. More importantly, the devices exhibit a fast switching response above 100 Hz. Our results demonstrate that such PSG gated TFTs take a great step for low-power flexible oxide electronics application.

Electric double layer gate controlled non-linear transport in a nanostructured functional perovskite oxide film

We report bipolar control of the non-linear drain-source current IDS in a field effect transistor made from a channel of a nanostructured film of a hole doped manganite using an electric double layer (EDL) gate. The EDL gate controls the depletion layer in the grain boundary region, leading to a control of the tunnelling process. A gate bias (VG≈±5V) modulates the IDS at room temperature by nearly ±40%. Correlation of the transient response of the gate and channel currents on application of a step-change in VG, establishes the role of the gate capacitor in the observed phenomena.

Electrostatic gating of metallic and insulating phases in SmNiO3 ultrathin films

The correlated electron system SmNiO3 exhibits a metal-insulator phase transition at 130 {\deg}C. Using an ionic liquid as an electric double layer (EDL) gate on three-terminal ultrathin SmNiO3 devices, we investigate gate control of the channel resistance and transition temperature. Resistance reduction is observed across both insulating and metallic phases with ~25% modulation at room temperature. We show that resistance modulation is predominantly due to electrostatic charge accumulation and not electrochemical doping by control experiments in inert and air en-vironments. We model the resistance behavior and estimate the accumulated sheet density (~1-2 x 10^14 cm^-2) and EDL capacitance (~12 {\mu}F/cm^2).

Organic solvents as gate media for thin-film transistors

Here, we show that some organic solvents can act as electric double layer (EDL) gate media for thin film transistors (TFTs), in a similar way to solid electrolytes, ionic liquids, and water. The ability to act as gate medium is a property of the solvent, not a property of the semiconductor used in the TFT. Only solvents that are fully miscible with water can act as a gate media. However, the ability to undergo autoprotolysis is not an essential property of a gate medium. The most likely explanation for the ability of water-miscible solvents to act as EDL gate media is the inevitable presence of trace amounts of dissolved salts. Because of its large electrochemical window, and aprotic character, acetonitrile is particularly attractive as an alternative gate medium.

Modeling Novel Double-in-Plane Gate Electric-Double-Layer Thin-Film and Nanoscale Transistors

A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thin-film transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm(2)). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner.

Modeling of low-voltage oxide-based electric-double-layer thin-film transistors fabricated at room temperature

The room-temperature-made low-voltage electric-double-layer (EDL) thin-film transistors (TFTs) are reported previously with good performance including a huge EDL gate capacitance above 1 μF/cm2. We report a two-dimensional simulation of the carrier transport and subgap density of states (DOS) in low-voltage indium tin oxide EDL TFTs. The simple model with a constant mobility and two-step subgap DOS reproduces well the characteristics of EDL TFTs. A nice fitting to the experimental data was obtained with a changeable effective conduction band DOS and valence band DOS model, which is reasonable to EDL electrostatic modulation mechanism. The EDL TFTs show much lower DOS than the InGaZnO4 TFTs.

Low-voltage transparent electric-double-layer ZnO-based thin-film transistors for portable transparent electronics

Room-temperature deposited 8.0 μm-thick mesoporous SiO2 dielectric shows a huge electric double layer (EDL) gate specific capacitance (4.16 μF/cm2). Battery drivable low-voltage (1.5 V) transparent EDL thin-film transistors (TFTs) with Al-doped ZnO nanocrystal channel layer gated by such dielectric are fabricated at room-temperature. The TFTs exhibit high-performance n-type transistor characteristics with a high field-effect mobility of 14.9 cm2/V s. The current on/off ratio and subthreshold gate voltage swing are estimated to be 2×106 and 82 mV/decade, respectively. Our results demonstrate that mesoporous SiO2 dielectrics with EDL effect are very promising for battery-powered portable transparent macroelectronics on temperature-sensitive substrates.