Efficient Test Sequences Research Articles

A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

Research on conformance test sequence generation of the communication unit adaptation specification protocol

The communication unit adaptation specification protocol of the customer-side energy measuring equipment and its conformance test is important for realizing massive equipment access to the energy internet flexibly and efficiently. The conformance test of communication protocol is the key to generating complete and efficient test sequences. In allusion to the problem of conformance test sequence generation of communication unit adaptation specification protocol, the paper first formally describes the protocol based on a finite state machine, and then further carries out the research on conformance test sequence generation based on T method, U method and U+ method. The results show that the test sequence generated by U+ method has the ability of state verification and the length is 22.1% shorter than that of U method. Its redundancy is slightly less than that of T method and the error detection ability is much better. Therefore, U+ method is more suitable for the conformance test sequence generation of communication unit adaptation specification protocol.

Research on automatic test sequence generation method of computer interlocking test

Railway computer interlocking system is the core equipment of station signal control system, which directly affects the reliability and safety of the whole system. It is essential to test the interlocking software comprehensively and strictly [1]. The traditional interlocking test is conducted by testers to control the quality and efficiency of the test. According to the reference railway transportation “Interim Measures for railway signal interlocking test”, combined with the signal interlocking relationship test checklist, compared with the actual station yard of railway station, relying on manual preparation and manual implementation of test items, the test efficiency is relatively low. Therefore, the realization of automatic interlocking test has become a research hotspot at present. Interlocking function test belongs to the research field of black box test. On the premise of ensuring the comprehensiveness of test, generating efficient test sequence is the research focus of this subject.

Employment of multiple algorithms for optimal path-based test selection strategy

Executing various sequences of system functions in a system under test represents one of the primary techniques in software testing. The natural way to create effective, consistent and efficient test sequences is to model the system under test and employ an algorithm to generate the tests that satisfy a defined test coverage criterion. Several criteria of test set optimality can be defined. In addition, to optimize the test set from an economic viewpoint, the priorities of the various parts of the system model under test must be defined. Using this prioritization, the test cases exercise the high priority parts of the system under test more intensely than those with low priority. Evidence from the literature and our observations confirm that finding a universal algorithm that produces an optimal test set for all test coverage and test set optimality criteria is a challenging task. Moreover, for different individual problem instances, different algorithms provide optimal results. In this paper, we present a path-based strategy to perform optimal test selection. The strategy first employs a set of current algorithms to generate test sets; then, it assesses the optimality of each test set by the selected criteria, and finally, chooses the optimal test set. The experimental results confirm the validity and usefulness of this strategy. For individual instances of 50 system under test models, different algorithms provided optimal results; these results varied by the required test coverage level, the size of the priority parts of the model, and the selected test set optimality criteria.

Directed Test Generation for Validation of Cache Coherence Protocols

Computing systems utilize multicore processors with complex cache coherence protocols to meet the increasing need for performance and energy improvement. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. In this paper, we propose an efficient test generation technique, which can be used to achieve full state and transition coverage in simulation-based verification for a wide variety of cache coherence protocols. Based on effective analysis of the state space structure, our method can generate more efficient test sequences (50% shorter) on-the-fly compared with tests generated by BFS. While our on-the-fly method can reduce the numbers of required tests by half, it can still be impractical to verify all possible transitions in the presence of large number of cores. We propose scalable on-the-fly test generation techniques using quotient state space. The proposed approach guarantees selection of important transitions by utilizing equivalence classes, and omits only similar transitions. Our experimental results demonstrate that our proposed approaches can efficiently tradeoff between transition coverage and validation effort.

Efficient Test Sequence Generator for Area Optimization in LFSR Reseeding

In this paper, a new concept of test pattern generator is used with Seed Initialization Method (SIM) for area optimization in LFSR reseeding. LFSR Reseeding is the method which is mainly used in logic BIST. Some of the reseeding mechanism needs some sort of memory to store all seeds. But this issue is overcome by present method. By this method, the proposed test pattern generator employs the output response of the CUT to the LFSR as the controlling signal to transform the LFSR state. It contains a net providing cell and LFSR with reversal logic to conform that there is no storage of seeds. When compared to previous methods, by using this approach (SIM), the test sequence that will have been given to LFSR is much reducing. The empirical outcome on ISCAS circuits shows that the conferred seed initialization method has brought reduced area overhead.

A novel intelligent verification platform based on a structured analysis model

An intelligent verification platform based on a structured analysis model is presented. Using an abstract model mechanism with specific signal interfaces for user callback, the unified structured analysis data, shared by the electronic system level design, functional verification, and performance evaluation, enables effi- cient management review, auto-generation of code, and modeling in the transaction level. We introduce the class tree, flow parameter diagram, structured flow chart, and event-driven finite state machine as structured analysis models. As a sand table to carry maps from different perspectives and levels via an engine, this highly reusable platform provides the mapping topology to search for unintended consequences and the graph theory for comprehensive coverage and smart test cases. Experimental results show that the engine generates efficient test sequences, with a sharp increase in coverage for the same vector count compared with a random test.

An Adaptive Efficient Test for Gumbel Domain of Attraction

We consider n independent observations, generated identically by some distribution function, which belongs to the domain of attraction of an extreme value distribution with unknown shape and scale parameter. We treat the scale parameter as a nuisance parameter and establish an adaptive efficient test sequence, which is based on the kn largest observations, for the Gumbel domain of attraction. Efficiency is achieved along certain contiguous extreme value alternatives within the concept of local asymptotic normality (LAN). Simulations exemplify the results

Generation of efficient test sequences from lotos specifications

AbstractLOTOS is a formal description technique (FDT) developed by ISO. This paper proposes a formal technique for generating test sequences from a LOTOS specification. In the proposed technique, test sequences correspond to a finite “tree” which is represented as a TreeLOTOS expression which is a subset of LOTOS. A labelled transition system (LTS) with variables called VTS is introduced to generate test sequences, which is useful not only for compactness of expression but also for effective selection of test sequences at the execution of tests. Furthermore, the concept of the reduced form of a VTS is introduced and, by using this concept, efficient test sequences can be obtained.

Diagnostic-strategy selection for series systems

The selection of efficient testing strategies for repairable systems composed of components arranged in series is considered. Two cost models (for perfect and imperfect testing) represent the consequences of possible test realizations. The probability that any particular component is responsible for the failure is derived and used as a basis for the two models. The model for perfect testing is solved exactly. In the optimal perfect-test sequence the components are tested in decreasing order of the ratio of: (probability that the component is responsible for the system failure) to (component test cost). For imperfect testing, possible diagnostic errors are included in a model for which two heuristic solution strategies are provided. The model represents the consequences of both false-positive and false-negative component-test outcomes. The heuristic strategies yield efficient test sequences. Under reasonable assumptions, the second heuristic strategy is guaranteed to locate the optimal test sequence. The model can quantitatively evaluate the benefits of test-accuracy enhancement plans. These models and algorithms provide convenient methods for selecting efficient test-sequences. This is illustrated by representative examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>