Efficient Software Implementation Research Articles

Fast-SNARF: A Fast Deformer for Articulated Neural Fields.

Neural fields have revolutionized the area of 3D reconstruction and novel view synthesis of rigid scenes. A key challenge in making such methods applicable to articulated objects, such as the human body, is to model the deformation of 3D locations between the rest pose (a canonical space) and the deformed space. We propose a new articulation module for neural fields, Fast-SNARF, which finds accurate correspondences between canonical space and posed space via iterative root finding. Fast-SNARF is a drop-in replacement in functionality to our previous work, SNARF, while significantly improving its computational efficiency. We contribute several algorithmic and implementation improvements over SNARF, yielding a speed-up of 150×. These improvements include voxel-based correspondence search, pre-computing the linear blend skinning function, and an efficient software implementation with CUDA kernels. Fast-SNARF enables efficient and simultaneous optimization of shape and skinning weights given deformed observations without correspondences (e.g. 3D meshes). Because learning of deformation maps is a crucial component in many 3D human avatar methods and since Fast-SNARF provides a computationally efficient solution, we believe that this work represents a significant step towards the practical creation of 3D virtual humans.

BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers

Low-precision quantized neural networks (QNNs) reduce the required memory space, bandwidth, and computational power, and hence are suitable for deployment in applications such as IoT edge devices. Mixed-precision QNNs, where weights commonly have lower precision than activations or different precision is used for different layers, can limit the accuracy loss caused by low-bit quantization, while still benefiting from reduced memory footprint and faster execution. Previous multiple-precision functional units supporting 8-bit, 4-bit, and 2-bit SIMD instructions have limitations, such as large area overhead, under-utilization of multipliers, and wasted memory space for low and mixed bit-width operations. This article introduces BISDU, a bit-serial dot-product unit to support and accelerate execution of mixed-precision low-bit QNNs on resource-constrained microcontrollers. BISDU is a multiplier-less dot-product unit, with frugal hardware requirements (a population count unit and 2:1 multiplexers). The proposed bit-serial dot-product unit leverages the conventional logical operations of a microcontroller to perform multiplications, which enables efficient software implementations of binary ( Xnor ), ternary ( Xor ), and mixed-precision [W×A] ( And ) dot-product operations. The experimental results show that BISDU achieves competitive performance compared to two state-of-the-art units, XpulpNN and Dustin, when executing low-bit-width CNNs. We demonstrate the advantage that bit-serial execution provides by enabling trading accuracy against weight footprint and execution time. BISDU increases the area of the ALU by 68% and the ALU power consumption by 42% compared to a baseline 32-bit RISC-V (RV32IC) microcontroller core. In comparison, XpulpNN and Dustin increase the area by 6.9× and 11.1× and the power consumption by 3.8× and 5.97×, respectively. The bit-serial state-of-the-art, based on a conventional popcount instruction, increases the area by 42% and power by 32%, with BISDU providing a 37% speedup over it.

A LIGHTWEIGHT ENCRYPTION ALGORITHM TO SECURE IOT DEVICES

Lightweight cryptography is an effective solution for ensuring confidentiality and privacy in resource-constrained environments, particularly in Internet of Things (IoT) systems. These systems consist of a large number of IoT devices, such as sensor nodes and embedded devices that handle sensitive data and are connected via the Internet, making them susceptible to various types of attacks. Considering the constrained processing capability, memory size, and energy of these devices, this article proposes a lightweight block cipher that aims to provide security for IoT devices, with a focus on achieving efficient software implementation, particularly in devices with 32-bit processors. The structural design of the suggested algorithm is based on Type-2 Generalized Feistel Networks (GFN), which are based on four branches of 32-bit and simple key scheduling. To enhance the diffusion and strength of the GFN structure, a partial permutation layer has been added to the cipher. Moreover, to reduce the implementation cost, a simple round function has been designed using low-cost operations like Addition, XOR, and Rotation. Security of the suggested algorithm has been validated through security analysis, and the results show meeting the criteria for avalanche effect with 50.97% Key Sensitivity and 50.58% Plaintext Sensitivity, and the correlation coefficienttest results indicate a weak correlation between the plaintext and ciphertext, this makes it difficult to retrieve the plaintext from the ciphertext. When designing lightweight algorithms, one of the primary objectives is to enhance performance. To evaluate the algorithm's performance, we tested its execution time, code size, memory consumption, and throughput on real IoT devices, such as ESP8266 and ESP32, as an embedded cryptographic module. Based on the experimental results and security analysis, the suggested algorithm showed a good grade of security and higher performance in encryption and decryption operations than other lightweight algorithms, which makes it capable of providing a framework for securing data in the restricted IoT environment.

Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers

The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to the nature of the hardware-friendly design of SPEEDY, the algorithm has low performance for software implementations. In particular, 6-bit S-box and bit permutation operations of SPEEDY are inefficient in software implementations, where it performs word-wise computations. We implemented the SPEEDY block cipher on a 32-bit microcontroller for the first time by applying the bit-slicing techniques. The optimized encryption performance results on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e., cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. In RISC-V, the performance showed 81.9, 95.5, and 109.2 clock cycles per byte, which outperformed the previous works. Finally, we conclude that SPEEDY can show efficient software implementation on low-end embedded environments.

Parallel Implementation of Sparse Distributed Memory for Semantic Storage

Introduction. Sparse Distributed Memory (SDM) and Binary Sparse Distributed Representations (Binary Sparse Distributed Representations, BSDR), as two phenomenological approaches to biological memory modelling, have many similarities. The idea of ??their integration into a hybrid semantic storage model with SDM as a low-level cleaning memory (brain cells) for BSDR, which is used as an encoder of high-level symbolic information, is natural. A hybrid semantic store should be able to store holistic data (for example, structures of interconnected and sequential key-value pairs) in a neural network. A similar design has been proposed several times since the 1990s. However, the previously proposed models are impractical due to insufficient scalability and/or low storage density. The gap between SDM and BSDR can be bridged by the results of a third theory related to sparse signals: Compressive Sensing or Sampling (CS). In this article, we focus on the highly efficient parallel implementation of the CS-SDM hybrid memory model for graphics processing units on the NVIDIA CUDA platform, analyze the computational complexity of CS-SDM operations for the case of parallel implementation, and offer optimization techniques for conducting experiments with big sequential batches of vectors. The purpose of the paper is to propose an efficient software implementation of sparse-distributed memory for preserving semantics on modern graphics processing units. Results. Parallel algorithms for CS-SDM operations are proposed, their computational complexity is estimated, and a parallel implementation of the CS-SDM hybrid semantic store is given. Optimization of vector reconstruction for experiments with sequential data batches is proposed. Conclusions. The obtained results show that the design of CS-SDM is naturally parallel and that its algorithms are by design compatible with the architecture of systems with massive parallelism. The conducted experiments showed high performance of the developed implementation of the SDM memory block. Keywords: GPU, CUDA, neural network, Sparse Distributed Memory, associative memory, Compressive Sensing.

Optimal synthesis into fixed XX interactions

We describe an optimal procedure, as well as its efficient software implementation, for exact and approximate synthesis of two-qubit unitary operations into any prescribed discrete family of XX-type interactions and local gates. This arises from the analysis and manipulation of certain polyhedral subsets of the space of canonical gates. Using this, we analyze which small sets of XX-type interactions cause the greatest improvement in expected infidelity under experimentally-motivated error models. For the exact circuit synthesis of Haar-randomly selected two-qubit operations, we find an improvement in estimated infidelity by 31.4% when including alongside CX its square- and cube-roots, near to the optimal limit of 36.9% obtained by including all fractional applications of CX.

Effective Pixel Rendering in Practice

The graphics processing unit (GPU) has now become an integral part of our lives through both desktop and portable devices. Thanks to dedicated hardware, visualization has been significantly accelerated, softwares today only use the GPU for rasterization. As a result of this development, now we use only triangle-based rendering, and pixel-based image manipulations can only be performed using shaders. It can be stated that today’s GPU pipeline cannot provide the same flexibility as the previous software implementation. This paper discusses an efficient software implementation of pixel-based rasterization. After reviewing the current GPU-based drawing process, we will show how to access pixel level drawing in this environment. Finally, a more efficient storage and display format than the classic solution is presented, which performance far exceeds the previous solution.

Entropy Balancing for Continuous Treatments

Abstract Interest in evaluating the effects of continuous treatments has been on the rise recently. To facilitate the estimation of causal effects in this setting, the present paper introduces entropy balancing for continuous treatments (EBCT) – an intuitive and user-friendly automated covariate balancing scheme – by extending the original entropy balancing methodology of Hainmueller, J. 2012. “Entropy Balancing for Causal Effects: A Multivariate Reweighting Method to Produce Balanced Samples in Observational Studies.” Political Analysis 20 (1): 25–46. In order to estimate balancing weights, the proposed approach solves a globally convex constrained optimization problem, allowing for computationally efficient software implementation. EBCT weights reliably eradicate Pearson correlations between covariates (and their transformations) and the continuous treatment variable. As uncorrelatedness may not be sufficient to guarantee consistent estimates of dose–response functions, EBCT also allows to render higher moments of the treatment variable uncorrelated with covariates to mitigate this issue. Empirical Monte-Carlo simulations suggest that treatment effect estimates using EBCT display favorable properties in terms of bias and root mean squared error, especially when balance on higher moments of the treatment variable is sought. These properties make EBCT an attractive method for the evaluation of continuous treatments. Software implementation is available for Stata and R.

The Rich Still Get Richer: Empirical Comparison of Preferential Attachment via Linking Statistics in Bitcoin and Ethereum

Bitcoin and Ethereum transactions present some of the largest real-world complex networks that are publicly available for study, including a detailed picture of their time evolution. As such, they have received a considerable amount of attention from the network science community along with analyses from economic and cryptographic perspectives. Among these studies, in an analysis on the early instance of the Bitcoin network, we have shown the clear presence of the preferential attachment, or the “rich-get-richer” phenomenon. Now, we revisit this question, using a recent version of the Bitcoin network that has grown almost 100-fold since our original analysis. Furthermore, we additionally carry out a comparison with Ethereum, the second most important cryptocurrency. Our results show that preferential attachment continues to be a key factor in the evolution of both the Bitcoin and Ethereum transactoin networks. To facilitate further analysis, we publish a recent version of both transaction networks, and an efficient software implementation that is able to evaluate linking statistics necessary for learn about preferential attachment on networks with several hundred million edges.

Modeling and Verification of ERP Functional Requirements based on Colored Petri Net

The rise of enterprise resource planning (ERP) systems has been a major event in the software industry and it became a solution for most enterprises to manage their data and business processes. Successful ERP implementations can reduce costs by improving efficiency then lead to improved company performance and better competitive edge. Despite these benefits and the age of ERP existing for several decades still high percentage of implementation failures are documented. ERP is packaged software designed by following the best practice from the specific industry to support typical business processes in the entire industrial field, it was designed by ERP vendors and used by the organization which implement it. Since the designer and user are two independent entity misalignments between user’s needs and the software design are often happen. The misalignment define new specific requirements must be embedded into selected ERP. Requirement engineering (RE) is a main part and initial activity of software engineering concern about defines stakeholder requirements, needs and desire. Requirements engineering is the basis for efficient software implementation and quality management. Tools and theories which support RE in general are numerous nowadays; however, the task of providing a tools and theories that specializes in Requirements engineering for Enterprise resource planning systems has been addressed rarely. For that; this paper discusses modelling and verification of ERP functional requirements based on colored Petri nets (CPN) after evaluation of different Business process modelling techniques by using analytical hierarchy process (AHP). CPN considered one of powerful business process modelling techniques and using it help in stakeholder involvement and appropriate organization’s business process representation. The nature of colored Petri nets that help in verification of internal completeness and consistency of ERP functional requirements model.

A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform

The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more importantly, the topology of the interconnection network is not easy to implement in VLSI due to the so-called retrograde indexing. Due to this problem, there are few pipeline implementations for IDCT and DCT, although pipelining is an efficient engineering solution that allows high speed performance with a reduced hardware complexity and power consumption. In this paper, we present an efficient solution to successfully reformulate the IDCT algorithm with a focus on developing a modular and regular computation structure that can be easily implemented using a pipelined VLSI architecture. Using new restructuring input sequences that can be computed in parallel with the new SFG graph in a pipeline manner, a novel efficient fast algorithm for the computation of inverse discrete cosine transform is presented. The obtained SFG graph has the best structure that can be obtained for IDCT, avoiding the so-called retrograde indexing and being highly regular and modular. Moreover, the obtained SFG graph is scalable, being easy to extend to larger values of N that is a power of 2. It can also be used to obtain a generalization of a radix-2 algorithm for length $$N = p \cdot 2^{m}$$ , where “p” is a prime number. This algorithm is based on a recursive decomposition of the computation of the inverse DCT that requires a reduced number of arithmetic operations and has a regular and simple computational structure that can be easily implemented in VLSI in a pipeline manner. Its main advantages are its simple, regular and modular computational structure and its high potential to be pipelined so that it can be used to obtain an efficient pipeline VLSI implementation.

Comprehensive Study of Coronavirus Disease 2019 (COVID-19) Classification based on Deep Convolution Neural Networks

Artificial Intelligence (AI) has recently become a topic of study in different applications, including healthcare, in which timely detection of anomalies can play a vital role in patients health monitoring. The coronavirus disease 2019 (COVID-19), caused by the SARS-CoV-2 virus, colloquially known as the Coronavirus, disrupts large parts of the world. The standard way to test for COVID-19 is Reverse Transcription Polymerase Chain Reaction (RT-PCR), which uses collected samples from the patient. This paper presents an efficient convolution neural network software implementation for COVID-19 and other pneumonia disease detection targeted for an AI-enabled smart biomedical diagnosis system (AIRBiS). From the evaluation results, we found that the classification accuracy of the abnormal (COVID-19 and pneumonia) test dataset is over 97.18%. On the other hand, the accuracy of the normal is no more than 71.37%. We discussed the possible problems and proposals for further optimization.

On the Efficient Evaluation of the Exchange Correlation Potential on Graphics Processing Unit Clusters.

The predominance of Kohn–Sham density functional theory (KS-DFT) for the theoretical treatment of large experimentally relevant systems in molecular chemistry and materials science relies primarily on the existence of efficient software implementations which are capable of leveraging the latest advances in modern high-performance computing (HPC). With recent trends in HPC leading toward increasing reliance on heterogeneous accelerator-based architectures such as graphics processing units (GPU), existing code bases must embrace these architectural advances to maintain the high levels of performance that have come to be expected for these methods. In this work, we purpose a three-level parallelism scheme for the distributed numerical integration of the exchange-correlation (XC) potential in the Gaussian basis set discretization of the Kohn–Sham equations on large computing clusters consisting of multiple GPUs per compute node. In addition, we purpose and demonstrate the efficacy of the use of batched kernels, including batched level-3 BLAS operations, in achieving high levels of performance on the GPU. We demonstrate the performance and scalability of the implementation of the purposed method in the NWChemEx software package by comparing to the existing scalable CPU XC integration in NWChem.

Application of incremental satisfiability problem solvers for non-deterministic polynomial-time hard problems as illustrated by minimal Boolean formula synthesis problem

Subject of Research. The paper considers a method for solution of the nondeterministic polynomial hard problem (NP-hard problem) of a minimal Boolean formula synthesis from a given truth table. The solution of this problem is proposed based on its reduction to the Boolean satisfiability problem (SAT). The issues of efficient and convenient software implementation are discussed for reducing nondeterministic polynomial hard problems to the satisfiability problem. Method. For a minimal Boolean formula synthesis, the constraint programming approach was used: a SATformula was created for a given truth table, satisfiable if and only if, there exists a Boolean formula of a given size that satisfies the given truth table. The developed method accent is the application of incremental satisfiability problem solvers. Main Results. A method is proposed for synthesis of a Boolean formula, minimal with respect to the number of operators and terminals, for a given truth table. The method is based on reducing to satisfiability problem and provides the usage of incremental satisfiability problem solvers. The kotlin-satlib framework is developed with the possibility to use the Kotlin and Java languages effectively and conveniently for the software implementation of reducing various nondeterministic polynomial-time hard problems to satisfiability problem. Native interaction with satisfiability problem solvers by Java Native Interface (JNI) technology is used. The proposed method for the minimal Boolean formula synthesis is implemented in the Kotlin programming language using the developed kotlin-satlib framework. Practical Relevance. An experimental study on the example of minimal Boolean formula synthesis has shown that the usage of incremental satisfiability problem solvers for nondeterministic polynomial hard problems is reasonable, since it reduces the total solving time in comparison with the non-incremental approach application.

Design of Symmetric-Key Primitives for Advanced Cryptographic Protocols

While traditional symmetric algorithms like AES and SHA3 are optimized for efficient hardware and software implementations, a range of emerging applications using advanced cryptographic protocols such as multi-party computation and zero-knowledge proofs require optimization with respect to a different metric: arithmetic complexity. In this paper we study the design of secure cryptographic algorithms optimized to minimize this metric. We begin by identifying the differences in the design space between such arithmetization-oriented ciphers and traditional ones, with particular emphasis on the available tools, efficiency metrics, and relevant cryptanalysis. This discussion highlights a crucial point --- the considerations for designing arithmetization-oriented ciphers are oftentimes different from the considerations arising in the design of software- and hardware-oriented ciphers. The natural next step is to identify sound principles to securely navigate this new terrain, and to materialize these principles into concrete designs. To this end, we present the Marvellous design strategy which provides a generic way to easily instantiate secure and efficient algorithms for this emerging domain. We then show two examples for families following this approach. These families --- Vision and Rescue --- are benchmarked with respect to three use cases: the ZK-STARK proof system, proof systems based on Rank-One Constraint Satisfaction (R1CS), and Multi-Party Computation (MPC). These benchmarks show that our algorithms achieve a highly compact algebraic description, and thus benefit the advanced cryptographic protocols that employ them. Evidence is provided that this is the case also in real-world implementations.

Design of Symmetric-Key Primitives for Advanced Cryptographic Protocols

While traditional symmetric algorithms like AES and SHA-3 are optimized for efficient hardware and software implementations, a range of emerging applications using advanced cryptographic protocols such as multi-party computation and zero knowledge proofs require optimization with respect to a different metric: arithmetic complexity.In this paper we study the design of secure cryptographic algorithms optimized to minimize this metric. We begin by identifying the differences in the design space between such arithmetization-oriented ciphers and traditional ones, with particular emphasis on the available tools, efficiency metrics, and relevant cryptanalysis. This discussion highlights a crucial point—the considerations for designing arithmetization-oriented ciphers are oftentimes different from the considerations arising in the design of software- and hardware-oriented ciphers.The natural next step is to identify sound principles to securely navigate this new terrain, and to materialize these principles into concrete designs. To this end, we present the Marvellous design strategy which provides a generic way to easily instantiate secure and efficient algorithms for this emerging domain. We then show two examples for families following this approach. These families — Vision and Rescue — are benchmarked with respect to three use cases: the ZK-STARK proof system, proof systems based on Rank-One Constraint Satisfaction (R1CS), and Multi-Party Computation (MPC). These benchmarks show that our algorithms achieve a highly compact algebraic description, and thus benefit the advanced cryptographic protocols that employ them.

FastField: An open-source toolbox for efficient approximation of deep brain stimulation electric fields

Deep brain stimulation (DBS) is a surgical therapy to alleviate symptoms of certain brain disorders by electrically modulating neural tissues. Computational models predicting electric fields and volumes of tissue activated are key for efficient parameter tuning and network analysis. Currently, we lack efficient and flexible software implementations supporting complex electrode geometries and stimulation settings. Available tools are either too slow (e.g. finite element method–FEM), or too simple, with limited applicability to basic use-cases. This paper introduces FastField, an efficient open-source toolbox for DBS electric field and VTA approximations. It computes scalable electric field approximations based on the principle of superposition, and VTA activation models from pulse width and axon diameter. In benchmarks and case studies, FastField is solved in about 0.2 s, ~ 1000 times faster than using FEM. Moreover, it is almost as accurate as using FEM: average Dice overlap of 92%, which is around typical noise levels found in clinical data. Hence, FastField has the potential to foster efficient optimization studies and to support clinical applications.

On the derivatives of set functions in matrix representation

This paper formalises the operations on capacities in matrix algebra framework. Various quantities that characterise the importance of the inputs and their dependencies are expressed through capacity derivatives, obtained through matrix–vector multiplication. Many relations between the set functions derivatives are established and found to be the consequences of the Divergence Theorem. New formulas for Shapley values and nonmodularity indices are found. The sums of the Shapley interaction indices are found to be related to lower order derivatives at the top and bottom elements of the respective power sets. The presented methods simplify many calculations and will facilitate efficient software implementations and applications of the capacity-based decision making methods.

A Reduced-Complexity Projection Algorithm for ADMM-Based LP Decoding

The alternating direction method of multipliers has recently been adapted for linear programming decoding of low-density parity-check codes. The computation of the projection onto the parity polytope is the core of this algorithm and usually involves a sorting operation, which is the main effort of the projection. In this paper, we present an algorithm with low complexity to compute this projection. The algorithm relies on new findings in the recursive structure of the parity polytope and iteratively fixes selected components. As shown in our realistic simulation setup, it requires up to 37% less arithmetical operations compared with state-of-the-art projections. Additionally, it does not involve a sorting operation, which is needed in all exact state-of-the-art projection algorithms. These two benefits make it appealing for efficient hardware and software implementations.

CGMBE: a model-based tool for the design and implementation of real-time image processing applications on CPU–GPU platforms

Processing large images in real time requires effective image processing algorithms as well as efficient software design and implementation to take full advantage of all CPU cores and GPU resources on state of the art CPU/GPU platforms. Efficiently coordinating computations on both the host (CPU) and devices (GPUs), along with host–device data transfers is critical to achieving real-time performance. However, such coordination is challenging for system designers given the complexity of modern image processing applications and the targeted processing platforms. In this paper, we present a novel model-based design tool that automates and optimizes these critical design decisions for real-time image processing implementation. The proposed tool consists of a compile-time static analyzer and a run-time dynamic scheduler. The tool automates the process of scheduling dataflow tasks (actors) and coordinating CPU–GPU data transfers in an integrated manner. The approach uses an unfolded dataflow graph representation of the application along with thread-pool-based executors, which are optimized for efficient operation on the targeted CPU–GPU platform. This approach automates the most complicated aspects of the design and implementation process for image processing system designers, while maximizing the utilization of computational power, reducing the memory footprint for both the CPU and GPU, and facilitating experimentation for tuning performance-oriented designs.