A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform

Abstract

The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more importantly, the topology of the interconnection network is not easy to implement in VLSI due to the so-called retrograde indexing. Due to this problem, there are few pipeline implementations for IDCT and DCT, although pipelining is an efficient engineering solution that allows high speed performance with a reduced hardware complexity and power consumption. In this paper, we present an efficient solution to successfully reformulate the IDCT algorithm with a focus on developing a modular and regular computation structure that can be easily implemented using a pipelined VLSI architecture. Using new restructuring input sequences that can be computed in parallel with the new SFG graph in a pipeline manner, a novel efficient fast algorithm for the computation of inverse discrete cosine transform is presented. The obtained SFG graph has the best structure that can be obtained for IDCT, avoiding the so-called retrograde indexing and being highly regular and modular. Moreover, the obtained SFG graph is scalable, being easy to extend to larger values of N that is a power of 2. It can also be used to obtain a generalization of a radix-2 algorithm for length $$N = p \cdot 2^{m}$$ , where “p” is a prime number. This algorithm is based on a recursive decomposition of the computation of the inverse DCT that requires a reduced number of arithmetic operations and has a regular and simple computational structure that can be easily implemented in VLSI in a pipeline manner. Its main advantages are its simple, regular and modular computational structure and its high potential to be pipelined so that it can be used to obtain an efficient pipeline VLSI implementation.