Efficient On-chip Communication Research Articles

AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip

Unlike conventional 2D Networks-on-Chip (NoCs), 3D NoCs offer a scalable and energy efficient on-chip communication. Vertical die stacking of 3D NoCs is enabled using inter-layer Through-Silicon Via (TSV) links. However, TSV technology suffers from low reliability and high fabrication costs. To mitigate these costs, Partially Connected 3D NoCs (PC-3DNoCs), which use fewer vertical TSV links, have been introduced. However, with fewer vertical links (a.k.a. elevators), elevator-less routers will have to send their traffic to nearby elevators for inter-layer traffic, increasing the traffic load and congestion at these elevators and potentially reducing performance. Therefore, it is important that elevator-less routers choose elevators that balance the traffic load among the available elevators. To address this problem, this paper presents an <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ad</u> aptive congestion- and energy-aware <underline xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ele</u> vator-selection algorithm, called AdEle+. AdEle+ employs an offline multi-objective simulated-annealing-based optimization to find good elevator subsets for routers. In addition, during high traffic loads, AdEle+ uses an adaptive and online elevator selection algorithm to select an elevator from the elevator subset to dynamically manage traffic congestion on elevators. Moreover, in low congestion circumstances, AdEle+ switches to a minimal distance selection to improve energy efficiency. Compared to state-of-the-art selection algorithms under various PC-3DNoC configurations and traffic patterns, AdEle+ reduces the average latency by 9.5% on average and up to 11.2% while reducing the hardware overhead by 10.1% due to its efficient online selection in the routers.

Broadband optical Ta2O5 antennas for directional emission of light.

Highly directive antennas with the ability of shaping radiation patterns in desired directions are essential for efficient on-chip optical communication with reduced cross talk. In this paper, we design and optimize three distinct broadband traveling-wave tantalum pentoxide antennas exhibiting highly directional characteristics. Our antennas contain a director and reflector deposited on a glass substrate, which are excited by a dipole emitter placed in the feed gap between the two elements. Full-wave simulations in conjunction with global optimization provide structures with an enhanced linear directivity as high as 119 radiating in the substrate. The high directivity is a result of the interplay between two dominant TE modes and the leaky modes present in the antenna director. Furthermore, these low-loss dielectric antennas exhibit a near-unity radiation efficiency at the operational wavelength of 780 nm and maintain a broad bandwidth. Our numerical results are in good agreement with experimental measurements from the optimized antennas fabricated using a two-step electron-beam lithography, revealing the highly directive nature of our structures. We envision that our antenna designs can be conveniently adapted to other dielectric materials and prove instrumental for inter-chip optical communications and other on-chip applications.

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks

With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy efficiency. The increase in connection density increases on-chip data movement, which makes efficient on-chip communication a critical function of the DNN accelerator. The contribution of this work is threefold. First, we illustrate that the point-to-point (P2P)-based interconnect is incapable of handling a high volume of on-chip data movement for DNNs. Second, we evaluate P2P and network-on-chip (NoC) interconnect (with a regular topology such as a mesh) for SRAM- and ReRAM-based in-memory computing (IMC) architectures for a range of DNNs. This analysis shows the necessity for the optimal interconnect choice for an IMC DNN accelerator. Finally, we perform an experimental evaluation for different DNNs to empirically obtain the performance of the IMC architecture with both NoC-tree and NoC-mesh. We conclude that, at the tile level, NoC-tree is appropriate for compact DNNs employed at the edge, and NoC-mesh is necessary to accelerate DNNs with high connection density. Furthermore, we propose a technique to determine the optimal choice of interconnect for any given DNN. In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN. We demonstrate that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.

TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture

Networks-on-chip (NoCs) are playing a critical role in modern multicore architecture, and NoC security has become a major concern. Maliciously implanted hardware Trojans (HTs) inject faults into on-chip communications that saturate the network, resulting in the leakage of sensitive data via side channels and significant performance degradation. While existing techniques protect NoCs by detecting and isolating HT-infected components, they inevitably incur occasional inaccurate detection with considerable network latency and power overheads. We propose TSA-NoC, a learning-based design framework for secure and efficient on-chip communication. The proposed TSA-NoC uses an artificial neural network for runtime HT-detection with higher accuracy. Furthermore, we propose a deep-reinforcement-learning-based adaptive routing design for HT mitigation with the aim of minimizing network latency and maximizing energy efficiency. Simulation results show that TSA-NoC achieves up to 97% HT-detection accuracy, 70% improved energy efficiency, and 29% reduced network latency as compared to state-of-the-art HT-mitigation techniques.

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures

With the increase in number and complexity of cores and components in Chip-Multiprocessors (CMP) and Systems-on-Chip (SoCs), a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network-on-Chip (NoC) has emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behaviour of NoCs by considering micro-architectural parameters of the underlying components to estimate performance, power and energy characteristics. Employing NoCs in three-dimensional integrated circuits (3D-ICs) can further improve performance, energy efficiency, and scalability characteristics of 3D SoCs and CMPs. Minimal error estimation of energy and performance of NoC components is crucial in architecture trade-off studies. Accurate modeling of re:Horizontal and vertical links by considering micro-architectural and physical characteristics reduces the error in power and performance estimation of 3D NoCs. Additionally, mapping the temperature distribution in a 3D NoC reduces estimation error.This paper presents the 3D NoC modelling capabilities extended in two existing state-of-the-art simulators, viz., the 2D NoC Simulator - BookSim2.0 and the thermal behaviour simulator - HotSpot6.0. With the extended 3D NoC modules, the simulators can be used for power, performance and thermal measurements through micro-architectural and physical parameters. The major extensions incorporated in BookSim2.0 are: Through Silicon Via power and performance models, 3D topology construction modules, 3D Mesh topology construction using variable X, Y, Z radix, tailored routing modules for 3D NoCs. The major extensions incorporated in HotSpot6.0 are: parameterized 2D router floorplan, 3D router floorplan including Through Silicon Vias (TSVs), power and thermal distribution models of 2D and 3D routers.Using the extended 3D modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using synthetic traffic patterns. Results show that the 4-layer 3D Mesh is 2.2 × better than 2-layer 3D Mesh and 4.5 × better than 3D BFT variants in terms of network latency. 3D Mesh variants have the lowest Energy Delay Product (EDP) compared to 3D BFT variants as there is an 80% reduction in link lengths and up to 3 × more TSVs. Another observation is that the EDP of the 4-layer 3D BFT (with transpose traffic) is 1.5 × the EDP of the 4-layer 3D Mesh (with transpose traffic). Further optimizations towards a tailored 3D BFT for transpose traffic could reduce this EDP gap with the 4-layer 3D Mesh. From the 3D NoC heat maps, it was found that the edge routers in the floorplan of the tested 3D Mesh and 3D BFT topologies have the least ambient temperature.

Research on homegrown manycore architecture for intelligent computing

In recent times, the demand for the computational capability of artificial intelligence (AI) is increasing rapidly. It is well-known that high parallelism algorithm and strong reusability of data provide more design space for processor architecture design. The manycore processor has a huge development space of AI with its strong on-chip computing power, flexible on-chip architecture, efficient on-chip communication, and flexible optimized storage. Based on the history of the development of manycore processors, this paper summarizes the main technical routes and focuses on the requirements of AI applications for the architecture and critical features of domestic manycore processors.

Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip

Networks-on-Chip (NoCs) are promising fabrics to provide scalable and efficient on-chip communication for large-scale many-core systems. In place of the well-studied synchronous NoCs, the event-driven asynchronous ones have emerged as promising replacement thanks to their strong timing robustness especially when implemented in quasi-delay-insensitive (QDI) circuits. However, their fault tolerance has rarely been studied. The QDI NoCs show complicated failure scenarios and behave differently from synchronous ones. As the scaling semiconductor technology is expected with the accelerated aging process, permanent faults become more likely to happen at runtime. These faults can break the handshake, leading to physical-layer deadlocks which can spread and paralyze the whole QDI NoC. This physical-layer deadlock cannot be resolved using conventional fault-tolerant or deadlock management techniques. This paper systematically studies the impact of permanent faults on QDI NoCs, and presents novel deadlock detection and recovery techniques to handle the fault-caused physical-layer deadlock. The proposed detection technique has been implemented to protect the NoC data paths that occupy ~90% of the logic. Employing the detection and recovery techniques to protect interrouter links (~60% of the logic), a permanently faulty link is precisely located and the network function can be recovered with graceful performance degradation.

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Today’s multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

Group based Shortest Path Routing Algorithm for Hierarchical Cross Connected Recursive Networks (HCCR)

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a Group-based Shortest Path Routing algorithm (GSR) for the HCCR. Network properties of HCCR are compared with Spidergon, THIN, 2-D Mesh and Hypercube. It is shown that the proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links, small diameter and low node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, based on which the GSR was developed. . The proposed addressing scheme divides the HCCR network into logical groups of same as well as different sizes. Packets move towards receiver using local or global routing. Simulations are performed to find all the possible shortest paths with GSR in HCCR networks (up to 1024 nodes). All the shortest paths produced by GSR are verified against Dijkstra’s algorithm. The GSR for k-level HCCR (L_k) with N= 〖4 〗^((2+k) )nodes, requires 5(k-1) time in the worst case to determine the next node along the shortest path. Average distance and frequency of hop counts of HCCR networks are investigated using GSR. The results are compared with average distance of 2-D Mesh. Experimental results show that with a network size of 1024 nodes, there is only a 7.7% increase in the average distance of L_3 HCCR in comparison to 2-D Mesh. However L_k have fewer paths with high hop count in comparison to 2-D Mesh.

On the design of hybrid routing mechanism for mesh-based network-on-chip

Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fixed cost based on information redundancy. TagNoC is a hybrid routing approach which combines the source and distributed routing methods together. While eliminating packet routing in each router, TagNoC determines the forwarding output port in parallel with input buffering. For a marginal cost increase in header size, as compared to distributed routing techniques, routing latency can be hidden while eliminating power consuming portion of the routing, increasing router throughput and decreasing latency. The proposed TagNoC router is compared to baseline router with distributed routing implementation on a 16-node CMP mesh. Physical implementation of all routers is modeled using synthesized RTL, detailed area analysis, and accurate channel models. Performance evaluation is also carried out utilizing RTL simulation and detailed power analysis on both synthetic and application traffic is performed using post-synthesis gate-level simulation. The simulation results illustrate that TagNoC outperforms as compared to baseline distributed architecture and other source routing methods in terms of power, latency, and throughput.

Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path.

Energy Efficient On-Chip Communications Implementation Based on Power Slacks

The quest for energy efficiency has growing importance in high performance many-core systems. However, in current practices, the power slacks, which are the differences observed between the input power budget and the actual power consumed in the many-core systems, are typically ignored, thus leading to poor energy efficiency. In this paper, we propose a scheme to effectively power the on-chip communications by exploiting the available power slack that is totally wasted in current many-core systems. As so, the demand for extra energy from external power sources (e.g., batteries) is minimized, which helps improve the overall energy efficiency. In essence, the power slack is stored at each node and the proposed routing algorithm uses a dynamic programming network to find the globally optimal path, along which the total energy stored on the nodes is the maximum. Experimental results have confirmed that the proposed scheme, with low hardware overhead, can reduce latency and extra energy consumption by 44% and 48%, respectively, compared with the two competing routing methods.

Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing

Network-on-Chip (NoC) is an efficient on-chip communication architecture specifically for System-on-a-Chip (SoC) design. However, the input buffers of a NoC router often take a significant portion of the silicon area and power consumption. Besides, the performance of a NoC is also greatly affected by the buffer size. In this article, a static buffer merging and resource sharing method is proposed for the application-specific SoC minimizing the NoC buffer. When given an application-specific task graph and the dataflow distribution, the proposed method statically merges rarely used buffers and generates the suitable number of input buffers for each router at design timely. The merged buffer is shared by several input directions. The experimental result shows that the buffer can be utilized more effectively after the resource sharing. Based on the synthesized design with TSMC 90nm technology, the proposed method reduces an average of 42.23% area and 35.13% power while providing similar performance.

Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques

Network on Chip is efficient on-chip communication architecture for system on chip architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC. The router architecture can be used for building a NoC with standard topology with low latency and high speed. In this paper, we implement and analyze a 3x3 mesh network configuration with routers which can support simultaneous routing requests, with blocking and non blocking inputs.

VBON: Toward efficient on-chip networks via hierarchical virtual bus

The need for scalable and efficient on-chip communication in future many-core architecture has resulted in the network-on-chip (NoC) design emerging as a popular solution. It is a common belief that packet-based NoC can provide high efficiency, high throughput, and low latency for future applications instead of conventional transaction-based bus. However, these superior features of NoCs are only applied to unicast (one-to-one) latency non-critical traffic. Their multi-hop feature and inefficient multicast (one-to-many) or broadcast (one-to-all) support have made it awkward when performing some kinds of communications including cache coherence protocol, global timing and control signals, and some latency critical communications. This paper presents VBON, a new architecture of incorporating buses into NoCs in order to take advantage of both NOCs and buses in a hierarchical way. The point-to-point links of conventional NoC designs can be used as bus transaction link dynamically for bus request. This can achieve low latency while sustain high throughput for both unicast and multicast communications at low cost. To reduce the latency of physical layout for the bus organization, the hierarchical redundant buses are used. Detailed network latency simulation and hardware characterization demonstrate that VBON can provide the ideal interconnect for a broad spectrum of unicast and multicast scenarios and achieve these benefits with inexpensive extensions to current NoC router.