Efficient Memory Access Patterns Research Articles

Sliding Window Sum Algorithms for Deep Neural Networks

Sliding window sums are widely used for string indexing, hashing and time series analysis. We have developed a family of the generic vectorized sliding sum algorithms that provide speedup of O(P/w) for window size w and number of processors P. For a sum with a commutative operator the speedup is improved to O(P/log(w)). Even more important, our algorithms exhibit efficient memory access patterns. In this paper we study the application of sliding sum algorithms to the training and inference of Deep Neural Networks. We demonstrate how both pooling and convolution primitives could be expressed as sliding sums and evaluated by the compute kernels with a shared structure. We show that the sliding sum convolution kernels are more efficient than the commonly used GEMM kernels on CPUs and could even outperform their GPU counterparts.

High quality rendering of protein dynamics in space filling mode

Producing high quality depictions of molecular structures has been an area of academic interest for years, with visualisation tools such as UCSF Chimera, Yasara and PyMol providing a huge number of different rendering modes and lighting effects. However, no visualisation program supports per-pixel lighting effects with shadows whilst rendering a molecular trajectory in space filling mode.In this paper, a new approach to rendering high quality visualisations of molecular trajectories is presented. To enhance depth, ambient occlusion is included within the render. Shadows are also included to help the user perceive relative motions of parts of the protein as they move based on their trajectories. Our approach requires a regular grid to be constructed every time the molecular structure deforms allowing per-pixel lighting effects and ambient occlusion to be rendered every frame, at interactive refresh rates. Two different regular grids are investigated, a fixed grid and a memory efficient compact grid.The algorithms used allow trajectories of proteins comprising of up to 300,000 atoms in size to be rendered at ninety frames per second on a desktop computer using the GPU for general purpose computations. Regular grid construction was found to only take up a small proportion of the total time to render a frame. It was found that despite being slower to construct, the memory efficient compact grid outperformed the theoretically faster fixed grid when the protein being rendered is large, owing to its more efficient memory access patterns. The techniques described could be implemented in other molecular rendering software.

Guest Editorial: Design and Implementation of DSP Systems

In recent years, there has been an increasing need to develop new implementation techniques and design methodologies for DSP systems. Algorithmic and architectural optimizations are key to developing high-performance signal and information processing systems under strict constraints on implementation complexity and power consumption. This special issue is composed of a selection of papers reporting on advances in the design and implementation of signal processing systems. The topics range from domainspecific hardware implementation to design methodologies for signal processing algorithm implementations. In BAn energy-efficient Reconfigurable ASIP supporting multi-mode MIMO detection,^ (10.1007/s11265-015-0972-x) Ahmad, Li, Amin, Li, Van der Perre, Lauwereins, and Pollin present a programmable ASIP MIMO baseband processor. They first present an efficient modification of the Multi-Tree Selective Spanning Detector algorithm. Then they introduce a soft-output algorithm for generating log-likelihood ratios, called counter-ML bit-flipping. A C-programmable ASIP is designed for 40 nm CMOS, operating at 3.6 Gbps for hard MIMO detection, and 2.05 Gbps for soft detection. Tripakis, Limaye, Ravindran, Wang, Andrade, and Ghosal consider models of dataflow computation in their paper BTokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware^ (10.1007/s11265-0150971-y). They define a formal conformance relation between finite state machines with synchronous semantics and a formal model for dataflow: asynchronous processes communicating via queues. The conformance can provide information in determining the accuracy of hardware models, can be used to highlight timing and synchronization errors, and derive performance properties. In BA dynamic modulo scheduling with binary translation: Loop optimization with software compatibility,^ (10.1007 /s11265-015-0974-8) Ferreira, Denver, Pereira, Wong, Lisboa, and Carro propose a binary translation technique for run-time modulo scheduling of loops onto course-grained reconfigurable arrays. The technique eliminates the need to generate an intermediate dataflow graph (DFG) and uses a greedy placement step. The experimental results show that the run-time technique can achieve higher instruction-level parallelism compared to a 16-issue VLIW processor. Akin, Franchetti, and Hoe present restructured Fast Fourier Transform (FFT) algorithms with efficient memory access patterns in their paper BFFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation^ (10.1007/s11265-015-1018-0). They use a formal representation of the FFT using the Kronecker product to automatically generate hardware implementations of DRAM-optimized FFT algorithms. Results for 1D, 2D, and 3D FFTs show that their designs can achieve close to the theoretical peak performance on several different platforms. In BAnalyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction,^ (10.1007/s11265-0150986-4) Mentzer, Paya-Vaya, and Blume consider the implementation of the Scale-Invariant Feature Transform (SIFT) used in computer vision. This complexity of the SIFT algorithm is too high for real-time implementation on * Warren J. Gross warren.gross@mcgill.ca

Highly optimized simulations on single- and multi-GPU systems of the 3D Ising spin glass model

We present a highly optimized implementation of a Monte Carlo (MC) simulator for the three-dimensional Ising spin-glass model with bimodal disorder, i.e., the 3D Edwards–Anderson model running on CUDA enabled GPUs. Multi-GPU systems exchange data by means of the Message Passing Interface (MPI). The chosen MC dynamics is the classic Metropolis one, which is purely dissipative, since the aim was the study of the critical off-equilibrium relaxation of the system. We focused on the following issues: (i) the implementation of efficient memory access patterns for nearest neighbours in a cubic stencil and for lagged-Fibonacci-like pseudo-Random Numbers Generators (PRNGs); (ii) a novel implementation of the asynchronous multispin-coding Metropolis MC step allowing to store one spin per bit and (iii) a multi-GPU version based on a combination of MPI and CUDA streams. Cubic stencils and PRNGs are two subjects of very general interest because of their widespread use in many simulation codes.

Real-time HD image distortion correction in heterogeneous parallel computing systems using efficient memory access patterns

High-definition video is becoming a standard in clinical endoscopy. State-of-the-art systems for medical endoscopy provide 1080p video streams at 60 Hz. For such high resolutions and frame rates, the real-time execution of image-processing tasks is far from trivial, requiring careful algorithm design and development. In this article, we propose a fully functional software-based solution for correcting the radial distortion (RD) of HD video that runs in real time in a personal computer (PC) equipped with a conventional graphics processing unit (GPU) and a video acquisition card. Our system acquires the video feed directly from the digital output of the endoscopic camera control unit, warps each frame using a heterogeneous parallel computing architecture, and outputs the result back to the display. Although we target the particular problem of correcting geometric distortion in medical endoscopy, the concepts and framework herein described can be extended to other image-processing tasks with hard real-time requirements. We show that a heterogeneous approach, as well as efficient memory access patterns in the GPU, improve the performance of this highly memory-bound algorithm, leading to frame rates above 250 fps.