Efficient Hardware Research Articles

Enabling low-latency IoT communication for resource-constrained devices with the led cipher and decipher protocol

Block cipher algorithms are crucial for securing applications on resource-constrained devices. This paper introduces the modified light encryption device (MLED) cipher-decipher architecture, specifically designed to accommodate both 64-bit and 128-bit key sizes while maintaining a consistent 64-bit block and data size. MLED comprises 8-step and 12-step processes for MLED-64 and MLED-128 modules, respectively. Each stage involves a four-round operation followed by an add-round key operation. The add constant module (ACM) and mixed column modules (MCMs) within the round operation have been optimized for improved latency and throughput. Performance analysis reveals that MLED-64/128 requires less than 1% of the available slices and operates at 125 MHz on the Artix-7 FPGA. It achieves delays of 7.5 and 12.5 clock cycles for MLED-64 and MLED-128, respectively, translating to throughputs of 1366.5 Mbps and 819.89 Mbps. Additionally, MLED-64/128 exhibits hardware efficiencies of 2.373 and 0.986 Mbps/slice, respectively. Comparative evaluations with existing LED and other block ciphers (BCs) demonstrate that MLED-64/128 achieves significant improvements in latency, throughput, and efficiency, making it a compelling choice for securing resource-constrained IoT applications.

HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Binary neural network (BNN), where both the weight and the activation values are represented with one bit, provides an attractive alternative to deploy highly efficient deep learning inference on resource-constrained edge devices. However, our investigation reveals that, to achieve satisfactory accuracy gains, state-of-the-art (SOTA) BNNs, such as FracBNN and ReActNet, usually have to incorporate various auxiliary floating-point components and increase the model size, which in turn degrades the hardware performance efficiency. In this article, we aim to quantify such hardware inefficiency in SOTA BNNs and further mitigate it with negligible accuracy loss. First, we observe that the auxiliary floating-point (AFP) components consume an average of 93% DSPs, 46% LUTs, and 62% FFs, among the entire BNN accelerator resource utilization. To mitigate such overhead, we propose a novel algorithm-hardware co-design, called FuseBNN , to fuse those AFP operators without hurting the accuracy. On average, FuseBNN reduces AFP resource utilization to 59% DSPs, 13% LUTs, and 16% FFs. Second, SOTA BNNs often use the compact MobileNetV1 as the backbone network but have to replace the lightweight 3 × 3 depth-wise convolution (DWC) with the 3 × 3 standard convolution (SC, e.g., in ReActNet and our ReActNet-adapted BaseBNN) or even more complex fractional 3 × 3 SC (e.g., in FracBNN) to bridge the accuracy gap. As a result, the model parameter size is significantly increased and becomes 2.25× larger than that of the 4-bit direct quantization with the original DWC (4-Bit-Net); the number of multiply-accumulate operations is also significantly increased so that the overall LUT resource usage of BaseBNN is almost the same as that of 4-Bit-Net. To address this issue, we propose HyBNN , where we binarize depth-wise separation convolution (DSC) blocks for the first time to decrease the model size and incorporate 4-bit DSC blocks to compensate for the accuracy loss. For the ship detection task in synthetic aperture radar imagery on the AMD-Xilinx ZCU102 FPGA, HyBNN achieves a detection accuracy of 94.8% and a detection speed of 615 frames per second (FPS), which is 6.8× faster than FuseBNN+ (94.9% accuracy) and 2.7× faster than 4-Bit-Net (95.9% accuracy). For image classification on the CIFAR-10 dataset on the AMD-Xilinx Ultra96-V2 FPGA, HyBNN achieves 1.5× speedup and 0.7% better accuracy over SOTA FracBNN.

Optimized wireless communication for 6G signal processing using memory‐augmented deep unfolding network

SummaryIn this manuscript, optimized wireless communication for 6G signals processing using memory‐augmented deep unfolding network (WC‐6G‐SP‐MADUN) is proposed. The aim of this work is to give a memory‐augmented deep unfolding network approach with a focus on belief propagation decoding of error correction codes and multiple‐input multiple‐output (MIMO) wireless systems. In contrast, compares and tabulates the performance of memory‐augmented deep unfolding methodologies with classic principled procedures, which could potentially enable 6G. Here, the wireless communication for 6G signal processing methods was used for a variety of receiver functions, including self‐interference cancelation, signal estimation and detection using memory‐augmented deep unfolding Network (MADUN), and advanced error correction by clouded leopard optimization algorithm (CLOA). Furthermore, outline the general framework of memory‐augmented deep unfolding method for any kind of signal processing application and talk about cutting edge research paths that will make it possible to build communication networks in the future. The proposed approach is implemented in MATLAB; the performance is analyzed with performance metrics such as reliability, complexity, SNR gain, convergence rate, hardware efficiency, and quantization bit width. The proposed approach attains higher SNR gain 17.96%, 24.75%, and 30.09%; lower complexity 17.92%, 23.41%, and 30.13%; and higher convergence 18.01%, 25.41%, and 31.39% when analyzed with existing techniques such as redefined wireless communication for 6G: signal processing meets deep learning and deep unfolding (RWC‐6G‐SP‐DU), lower complication deep unfolded neural network receiver for MIMO under probability data association detector (LC‐DUNN‐MIMO‐PDAD), and deep learning in physical layer communications: evolution with prospects on 5G and 6G networks (DL‐PLC‐6G), respectively.

Multilayer Neural Network Hardware Designs for Faster Convolutional Processing

The demand for efficient hardware implementations of convolutional neural networks (CNNs) has surged with the proliferation of deep learning applications in various domains such as computer vision, natural language processing, and autonomous systems. Convolutional layers, being the fundamental building blocks of CNNs, are computationally intensive, requiring optimized hardware architectures for real-time inference tasks. This paper presents novel hardware designs targeting faster convolutional processing within multilayer neural networks. We propose a multi-faceted approach that leverages parallelism, pipelining, and hardware acceleration techniques to enhance the efficiency of convolution operations. Our design optimally exploits the inherent data-level and model-level parallelism present in CNNs to achieve high throughput while minimizing latency.

An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs

Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

On the Performance of MMSE Channel Estimation in Massive MIMO Systems over Spatially Correlated Rician Fading Channels

Massive multiple-input-multiple-output (M-MIMO) offers remarkable advantages in terms of spectral, energy, and hardware efficiency for future wireless systems. However, its performance relies on the accuracy of channel state information (CSI) available at the transceivers. This makes channel estimation pivotal in the context of M-MIMO systems. Prior research has focused on evaluating channel estimation methods under the assumption of spatially uncorrelated fading channel models. In this study, we evaluate the performance of the minimum-mean-square-error (MMSE) estimator in terms of the normalized mean square error (NMSE) in the uplink of M-MIMO systems over spatially correlated Rician fading. The NMSE allows for easy comparison of different M-MIMO configurations, serving as a relative performance indicator. Besides, it is an advantageous metric due to its normalization, scale invariance, and consistent performance indication across diverse scenarios. In the system model, we assume imperfections in channel estimation and that the random angles in the correlation model follow a Gaussian distribution. For this scenario, we derive an accurate closed-form expression for calculating the NMSE, which is validated via Monte-Carlo simulations. Our numerical results reveal that as the Rician K-factor decreases, approaching Rayleigh fading conditions, the NMSE improves. Additionally, spatial correlation and a reduction in the antenna array interelement spacing lead to a reduction in NMSE, further enhancing the overall system performance.

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts.

AN OVERVIEW OF COMPONENTS FOR ENERGY EFFICIENT MULTIMEDIA NETWORKS BASED ON 5G RADIO ACCESS TECHNOLOGIES

Modern society is actively transitioning into an information-based one, and multimedia technologies have become an integral part of this process. Thanks to the proliferation of wireless access networks, users are becoming more mobile, and the development of the fifth generation of mobile networks, known as 5G, is a significant step in the advancement of information and communication technologies. 5G networks offer low latency and reliable connectivity, expanding the capabilities of mobile internet and machine communication. However, along with the opportunities provided by multimedia communication, there is a responsibility to consider the impact of associated technologies on the environment, as well as to address new challenges and the need for prudent resource utilization.
 The article defines the concept of "multimedia" and discusses various aspects of this concept, including digital storage and processing of information, components (text, photos, audio, and video), interactivity, and hypertextuality. It is noted that the transmission of multimedia data and the use of information technologies are closely linked to wireless access networks.
 The authors discuss challenges and solutions in the field of energy efficiency for networks. They provide statistics indicating that the information and communication technology (ICT) industry is responsible for a significant portion of global energy consumption and CO2 emissions, with radio access networks being a major contributor. Various components and technologies that can contribute to the development of energy-efficient multimedia networks based on 5G radio access technologies are examined. Specifically, heterogeneous networks, non-orthogonal multiple access (NOMA) technologies, and multiple-input multiple-output (MIMO) technologies are highlighted as key components for achieving energy efficiency.
 The importance of using heterogeneous networks to reduce the distance between transmitters and receivers is emphasized, along with the possibility of putting small base stations into sleep mode when there is no network load. Technologies like NOMA and MIMO are discussed as crucial components for achieving spectral efficiency and energy efficiency.
 Additionally, the article focuses on wireless sensor networks (WSNs) and suggests ways to optimize them for energy efficiency. This includes operating sensor units only when necessary, implementing wireless charging, using energy-efficient optimization methods, and applying efficient routing schemes.
 The authors also highlight the role of green data centers in reducing CO2 emissions and optimizing the use of green energy in high-performance networks. Methods such as using renewable energy sources, increasing the energy efficiency of hardware, and implementing energy-efficient routing are discussed.
 In conclusion, the article underscores the importance of energy efficiency and reduced CO2 emissions in modern multimedia networks, particularly in the context of 5G networks. It calls for interdisciplinary efforts to address these critical challenges in the field of information and communication technologies.

CNC: A lightweight architecture for Binary Ring-LWE based PQC

In lattice-based cryptography, Ring Learning with Errors (RLWE) is a computationally hard cryptographic problem, comprising three basic mechanisms i.e., key generation, encryption, and decryption. Binary Ring Learning with Error (BRLWE), a new variant of RLWE has been proposed recently to reduce the key size and computational complexity compared to previous RLWE-based schemes. Based on this BRLWE scheme, efficient hardware architectures have been obtained in recent works for lightweight applications. The key operation involved in this scheme is AB+C , where A and C are integer polynomials and B is a binary polynomial. This paper proposes an efficient hardware architecture for BRLWE-based scheme targeted for lightweight applications. The architecture computes the arithmetic operation AB+C, which includes polynomial multiplication and addition over the polynomial ring Zq/(xn+1). The proposed architecture is applied in two conditions, fixed and variable values of q. Experimental results show the architecture proposed has 50% less Area-Delay Product (ADP) and 20% less Power-Delay Product (PDP) compared to the recently reported work for n=256.

Resource Efficient Deep Learning Hardware Watermarks with Signature Alignment

Deep learning intellectual properties (IPs) are high-value assets that are frequently susceptible to theft. This vulnerability has led to significant interest in defending the field's intellectual properties from theft. Recently, watermarking techniques have been extended to protect deep learning hardware from privacy. These technique embed modifications that change the hardware's behavior when activated. In this work, we propose the first method for embedding watermarks in deep learning hardware that incorporates the owner's key samples into the embedding methodology. This improves our watermarks' reliability and efficiency in identifying the hardware over those generated using randomly selected key samples. Our experimental results demonstrate that by considering the target key samples when generating the hardware modifications, we can significantly increase the embedding success rate while targeting fewer functional blocks, decreasing the required hardware overhead needed to defend it.

Gated Attention Coding for Training High-Performance and Efficient Spiking Neural Networks

Spiking neural networks (SNNs) are emerging as an energy-efficient alternative to traditional artificial neural networks (ANNs) due to their unique spike-based event-driven nature. Coding is crucial in SNNs as it converts external input stimuli into spatio-temporal feature sequences. However, most existing deep SNNs rely on direct coding that generates powerless spike representation and lacks the temporal dynamics inherent in human vision. Hence, we introduce Gated Attention Coding (GAC), a plug-and-play module that leverages the multi-dimensional gated attention unit to efficiently encode inputs into powerful representations before feeding them into the SNN architecture. GAC functions as a preprocessing layer that does not disrupt the spike-driven nature of the SNN, making it amenable to efficient neuromorphic hardware implementation with minimal modifications. Through an observer model theoretical analysis, we demonstrate GAC's attention mechanism improves temporal dynamics and coding efficiency. Experiments on CIFAR10/100 and ImageNet datasets demonstrate that GAC achieves state-of-the-art accuracy with remarkable efficiency. Notably, we improve top-1 accuracy by 3.10% on CIFAR100 with only 6-time steps and 1.07% on ImageNet while reducing energy usage to 66.9% of the previous works. To our best knowledge, it is the first time to explore the attention-based dynamic coding scheme in deep SNNs, with exceptional effectiveness and efficiency on large-scale datasets. Code is available at https://github.com/bollossom/GAC.

Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses

Indirect memory accesses (IMAs, i.e., A [ f ( B [ i ])]) are typical memory access patterns in applications such as graph analysis, machine learning, and database. IMAs are composed of producer-consumer pairs, where the consumers’ memory addresses are derived from the producers’ memory data. Due to the built-in value-dependent feature, IMAs exhibit poor locality, making prefetching ineffective. Hindered by the challenges of recording the potentially complex graphs of instruction dependencies among IMA producers and consumers, current state-of-the-art hardware prefetchers either (a) exhibit inadequate IMA identification abilities or (b) rely on the run-ahead mechanism to prefetch IMAs intermittently and insufficiently. To solve this problem, we propose Tyche, 1 an efficient and general hardware prefetcher to enhance IMA performance. Tyche adopts a bilateral propagation mechanism to precisely excavate the instruction dependencies in simple chains with moderate length (rather than complex graphs). Based on the exact instruction dependencies, Tyche can accurately identify various IMA patterns, including nonlinear ones, and generate accurate prefetching requests continuously. Evaluated on broad benchmarks, Tyche achieves an average performance speedup of 16.2% over the state-of-the-art spatial prefetcher Berti. More importantly, Tyche outperforms the state-of-the-art IMA prefetchers IMP, Gretch, and Vector Runahead, by 15.9%, 12.8%, and 10.7%, respectively, with a lower storage overhead of only 0.57 KB.

LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics

This work presents a novel reconfigurable architecture for Low Latency Graph Neural Network (LL-GNN) designs for particle detectors, delivering unprecedented low latency performance. Incorporating FPGA-based GNNs into particle detectors presents a unique challenge since it requires sub-microsecond latency to deploy the networks for online event selection with a data rate of hundreds of terabytes per second in the Level-1 triggers at the CERN Large Hadron Collider experiments. This article proposes a novel outer-product based matrix multiplication approach, which is enhanced by exploiting the structured adjacency matrix and a column-major data layout. In addition, we propose a custom code transformation for the matrix multiplication operations, which leverages the structured sparsity patterns and binary features of adjacency matrices to reduce latency and improve hardware efficiency. Moreover, a fusion step is introduced to further reduce the end-to-end design latency by eliminating unnecessary boundaries. Furthermore, a GNN-specific algorithm-hardware co-design approach is presented which not only finds a design with a much better latency but also finds a high accuracy design under given latency constraints. To facilitate this, a customizable template for this low latency GNN hardware architecture has been designed and open-sourced, which enables the generation of low-latency FPGA designs with efficient resource utilization using a high-level synthesis tool. Evaluation results show that our FPGA implementation is up to 9.0 times faster and achieves up to 13.1 times higher power efficiency than a GPU implementation. Compared to the previous FPGA implementations, this work achieves 6.51 to 16.7 times lower latency. Moreover, the latency of our FPGA design is sufficiently low to enable deployment of GNNs in a sub-microsecond, real-time collider trigger system, enabling it to benefit from improved accuracy. The proposed LL-GNN design advances the next generation of trigger systems by enabling sophisticated algorithms to process experimental data efficiently.

A Compact Hardware Design and Implementation on FPGA Based Hybrid of AES and Keccak SHA3-512 for Enhancing Data Security

Data security means protecting important information from unauthorised persons. In a security system, cryptography is the most secure method. Cryptography has many kinds, but the Advanced Encryption Standard (AES) is the most secure system. If combined with AES and Secure Hash Algorithm-3-512Bits (SHA3-512), it becomes compact, more secure, and more authenticated for data communications. The proposed methodology is a hybrid cryptography technique that combines AES with the SHA3-512 algorithm. This system becomes a strong, secure system and produces a strong cipher text. The proposed method AES/SHA3-512 is Hardware implementation on the Artix-7 FPGA family yields the lowest cost and highest hardware efficiency with a reduction in area usage of LUT 18.49%, Flip Flops 0.83%, and IO 3.8%. The proposed architecture is synthesised and simulated using the Vivado 2017.2 version Tool.

Compact Circuits for Efficient Möbius Transform

The Möbius transform is a linear circuit used to compute the evaluations of a Boolean function over all points on its input domain. The operation is very useful in finding the solution of a system of polynomial equations over GF(2) for obvious reasons. However the operation, although linear, needs exponential number of logic operations (around n · 2n−1 bit xors) for an n-variable Boolean function. As such, the only known hardware circuit to efficiently compute the Möbius Transform requires silicon area that is exponential in n. For Boolean functions whose algebraic degree is bound by some parameter d, recursive definitions of the Möbius Transform exist that requires only O(nd+1) space in software. However converting the mathematical definition of this space-efficient algorithm into a hardware architecture is a non-trivial task, primarily because the recursion calls notionally lead to a depth-first search in a transition graph that requires context switches at each recursion call for which straightforward mapping to hardware is difficult. In this paper we look to overcome these very challenges in an engineering sense. We propose a space efficient sequential hardware circuit for the Möbius Transform that requires only polynomial circuit area (i.e. O(nd+1)) provided the algebraic degree of the Boolean function is limited to d. We show how this circuit can be used as a component to efficiently solve polynomial equations of degree at most d by using fast exhaustive search. We propose three different circuit architectures for this, each of which uses the Möbius Transform circuit as a core component. We show that asymptotically, all the solutions of a system of m polynomials in n unknowns and algebraic degree d over GF(2) can be found using a circuit of silicon area proportional to m · nd+1 and circuit depth proportional to 2 · log2(n − d).In the second part of the paper we introduce a fourth hardware solver that additionally aims to achieve energy efficiency. The main idea is to reduce the solution space to a small enough value by parallel application of Möbius Transform circuits over the first few equations of the system. This is done so that one can check individually whether the vectors of this reduced solution space satisfy each of the remaining equations of the system using lower power consumption. The new circuit has area also bound by m · nd+1 and has circuit depth proportional to d · log2 n. We also show that further optimizations with respect to energy consumption may be obtained by using depth-bound Möbius circuits that exponentially decrease run time at the cost of additional logic area and depth.

Colorful image reconstruction from neuromorphic event cameras with biologically inspired deep color fusion neural networks.

Neuromorphic event-based cameras communicate transients in luminance instead of frames, providing visual information with a fine temporal resolution, high dynamic range and high signal-to-noise ratio. Enriching event data with color information allows for the reconstruction of colorful frame-like intensity maps, supporting improved performance and visually appealing results in various computer vision tasks. In this work, we simulated a biologically inspired color fusion system featuring a three-stage convolutional neural network for reconstructing color intensity maps from event data and sparse color cues. While current approaches for color fusion use full RGB frames in high resolution, our design uses event data and low-spatial and tonal-resolution quantized color cues, providing a high-performing small model for efficient colorful image reconstruction. The proposed model outperforms existing coloring schemes in terms of SSIM, LPIPS, PSNR, and CIEDE2000 metrics. We demonstrate that auxiliary limited color information can be used in conjunction with event data to successfully reconstruct both color and intensity frames, paving the way for more efficient hardware designs.

A Progressive Subnetwork Searching Framework for Dynamic Inference.

Deep neural network (DNN) model compression is a popular and important optimization method for efficient and fast hardware acceleration. However, the compressed model is usually fixed, without the capability to tune the computing complexity (i.e., latency in hardware) on-the-fly, depending on dynamic latency requirements, workloads, and computing hardware resource allocation. To address this challenge, dynamic DNN with run-time adaption of computing structures has been constructed through training with a cross-entropy objective function consisting of multiple subnets sampled from the supernet. Our investigations in this work show that the performance of dynamic inference highly relies on the quality of subnet sampling. To construct a dynamic DNN with multiple high-quality subnets, we propose a progressive subnetwork searching framework, which is embedded with several proposed new techniques, including trainable noise ranking, channel-group sampling, selective fine-tuning, and subnet filtering. Our proposed framework empowers the target dynamic DNN with higher accuracy for all the subnets compared with prior works on both the Canadian Institute for Advanced Research dataset with 10 classes (CIFAR-10) and ImageNet datasets. Specifically, compared with United States-Neural Network (US-NN), our method achieves 0.9% average accuracy gain for Alexnet, 2.5% for ResNet18, 1.1% for Visual Geometry Group (VGG)11, and 0.58% for MobileNetv1, on the ImageNet dataset, respectively. Moreover, to demonstrate run-time tuning of computing latency of dynamic DNN in real computing system, we have deployed our constructed dynamic networks into Nvidia Titan graphics processing unit (GPU) and Intel Xeon central processing unit (CPU), showing great improvement over prior works. The code is available at https://github.com/ASU-ESIC-FAN-Lab/Dynamic-inference.

An Efficient Method and Hardware System for Monitoring of Illegal Logging Events in Forest

An Efficient Method and Hardware System for Monitoring of Illegal Logging Events in Forest

CHEAT DETECTION IN ONLINE EXAMINATIONS USING ARTIFICIAL INTELLIGENCE

With increasing use of ICT and technical advancements in the education sector, distant and online education as well as examinations are being carried out frequently. However, online examination, as a method of assessment offers the risk of an unmonitored setting where students have full access to external resources. Online-proctored exams are the most efficient way for educational institutions to ensure academic honesty and ethics to counteract this. Typically, proctoring requires human assistance in the form of online proctors who remotely monitor students' performance. Yet, due to the rising demand for personnel and the intrusive nature of human proctoring, it is imperative to explore other areas. To tackle this pressing issue, this research work aims to devise a novel architecture that, through the development of a robust and automated Artificial Intelligence system, enables students to take exams remotely and reduces proctor involvement. The method overcomes the shortcomings of the previous automated proctoring system by combining important components of online exam cheating detection with cost-effective and efficient hardware. By proposing a Hybrid of FaceNet Model, Lucas Kanade Algorithm, and Active Appearance Model for Face Detection and Activity Monitoring of the student, the proposed system extracts semantic indicators to evaluate whether an applicant is cheating in an online examination. The proposed Cheat Detection system's experimental results measured via an F-score of 0.94 demonstrate its efficacy, and promising performance compared to the standard baseline techniques.

SC-IZ: A Low-Cost Biologically Plausible Izhikevich Neuron for Large-Scale Neuromorphic Systems Using Stochastic Computing

Neurons are crucial components of neural networks, but implementing biologically accurate neuron models in hardware is challenging due to their nonlinearity and time variance. This paper introduces the SC-IZ neuron model, a low-cost digital implementation of the Izhikevich neuron model designed for large-scale neuromorphic systems using stochastic computing (SC). Simulation results show that SC-IZ can reproduce the behaviors of the original Izhikevich neuron. The model is synthesized and implemented on an FPGA. Comparative analysis shows improved hardware efficiency; reduced resource utilization, which is a 56.25% reduction in slices, 57.61% reduction in Look-Up Table (LUT) usage, and a 58.80% reduction in Flip-Flop (FF) utilization; and a higher operating frequency compared to state-of-the-art Izhikevich implementation.