Effects Of Hot-carrier Stress Research Articles

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

Analysis of Contrasting Degradation Behaviors in Channel and Drift Regions Under Hot Carrier Stress in PDSOI LD N-Channel MOSFETs

This letter studies the effects of hot carrier stress (HCS) in laterally diffused silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors. After HCS, threshold voltage and subthreshold swing degrade, while the ON-state current exhibits degradation after an abnormal spike due to hole trapping in the resist-protective oxide. Impact ionization simulation shows that low doping concentrations in the drift region cause a severe Kirk effect under HCS and more severe degradation at higher gate voltages. However, degradation in the channel contrasts with the simulation result, which suggests an additional mechanism. Variable temperature HCS confirms that channel degradation is instead dominated by temperature.

Effects of Hot-Carrier Stress on the RF Performance of a 0.18-μm MOS Divide-by-4 LC Injection-Locked Frequency Divider

The effect of ac hot-carrier stress on the performance of a wide locking range divide-by-4 injection-locked frequency divider (ILFD) is investigated. The ILFD was implemented in the TSMC 0.18 μm 1P6M CMOS process. The ILFD uses direct injection MOSFETs for coupling external signal to the resonators. Radio frequency (RF) circuit parameters such as oscillation frequency, tuning range, phase noise, and locking range before and after RF stress at an elevated supply voltage for 5 h have been examined by experiment. The measured locking range, operation range and phase noise after RF stress shows significant degradation from the fresh circuit condition.

Gate voltage dependence on hot carrier degradation at an elevated temperature in a device with ultrathin silicon oxynitride

The effects of hot carrier stress (HCS) at elevated temperature on a device with ultrathin silicon oxynitride have been investigated. It was shown that the degradation of the device was more significant at elevated temperature compared with at room temperature. This behavior attributed to more generation of interface states due to an increase in the high-energy tail electrons. By the theory of electron-electron scattering, the threshold voltage shift was the most severe at the condition of VG>VD. However, based on the results of extrapolating the device lifetime, the worst case stress condition under HCS was the VG=VD condition at elevated temperature due to a higher generation rate.

Effects of hot-carrier stress on high performance polycrystalline silicon thin film transistor with a single perpendicular grain boundary

This paper is a report on the effect of a single perpendicular grain boundary on the hot-carrier and high current stability in high performance polycrystalline silicon (poly-Si) thin film transistors (TFTs). Under a hot carrier stress condition (Vg = Vth + 1 V, Vd = 12 V), the poly-Si TFT with a single grain boundary is superior to the poly-Si without any grain boundary because of the smaller free carriers available for electric conduction. The shift of transconductance in poly-Si TFT with a single grain boundary is less than 5% after hot carrier stress during a period of 1000 s. The shift of transconductance is about 25% in the case of the poly-Si TFTs without a grain boundary in the channel. On high current stress, the poly-Si TFT without the grain boundary is less degraded than the poly-Si TFT with the grain boundary because the concentrated electric field near the drain junction is lower.

HOT CARRIER EFFECTS ON JITTER PERFORMANCE IN CMOS VOLTAGE-CONTROLLED OSCILLATORS

The effects of hot carrier stress on CMOS voltage-controlled oscillators (VCO) are investigated. A model of the threshold voltage degradation in MOSFETs due to hot carrier stress has been used to model jitter in voltage-controlled oscillators. The relation between the stress time which induces the hot carrier effects due to generation of interface traps near the drain of the n-MOSFETs, and the degradation of the VCO performance is presented. The VCO performance degradation takes into consideration decrease in operation frequency and increase in jitter. The experimental circuits have been designed in 0.5 μm n-well CMOS technology for operation at 3 V. Experimental results show that after four hours hot-carrier stress the jitter is increased by 40 ps for single-ended current starved VCOs.

Effects of hot-carrier stress on the performance of CMOS low-noise amplifiers

The effects of direct current (dc) hot-carrier stress on the characteristics of NMOSFETs and a fully integrated low-noise amplifier (LNA) made of NMOSFETs in an 0.18-/spl mu/m complementary MOS (CMOS) technology are investigated. The increase in threshold voltage and decrease in mobility caused by hot carriers lead to a drop in the biasing current of the transistors. These effects lead to a decrease in the transconductance and an increase of the output conductance of the device. No measurable change in the parasitic gate-source and gate-drain capacitances in the devices under test were observed due to hot carriers. In the LNA, the important effects caused by hot carriers were a drop of the power gain and an increase of the noise figure. A slight increase in the input and output matching S/sub 11/ and S/sub 22/, respectively, after hot-carrier stress was observed. The linearity parameter IIP3 of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the I-V characteristics of the transistors in the LNA at the particular operating point where the measurements were performed.

Hot-carrier reliability of submicron NMOSFETs and integrated NMOS low noise amplifiers

The effects of hot-carrier stress (HCS) on the performance of NMOSFETs and a fully integrated low noise amplifier (LNA) made of NMOSFETs in a 0.18 μm CMOS technology are studied. The main effects of HCS on single NMOSFETs are an increase in threshold voltage and a decrease in channel carrier mobility, which lead to a drop in the biasing current of the transistors. In the small-signal model of the transistor, hot-carrier effects appear as a decrease in the transconductance and an increase of the output conductance. No clear change was observed in the parasitic gate–source and gate–drain capacitances in the devices under test due to hot carriers. The main effects of hot carriers in the LNA were a drop of the power gain and an increase of its noise figure. The input and output matching, S 11 and S 22, slightly increased after hot-carrier stress. The third- order input-referred intercept point (IIP3) of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the current–voltage ( I–V) characteristics of the transistors in the LNA at the particular operating point where they were biased.

Degradation of Low-Frequency Noise in Partially Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors by Hot-Carrier Stress

In this study, we determined the effects of hot-carrier stress on the low-frequency noise characteristics of partially depleted metal–oxide–semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator (SOI) technology. In devices with a floating-body configuration, kink-related excess noise was observed due to the floating-body effect. The level of this excess noise decreased after normal-mode stress, while it was masked by 1/ f noise after reverse-mode stress. The effects of stress-generated interface traps on the drain-to-body leakage current and the floating-body effect were also determined and used to explain the noise behavior. Moreover, the stress-induced 1/ f noise degradation in floating-body devices and body-contact devices was studied. It was found that the 1/ f degradation of body-contact devices is more significant than that of floating-body devices after hot-carrier stress.

Modeling of Degradation Effects on the High Frequency Noise of Metal–Oxide–Semiconductor Field-Effect Transistors

This paper proposes a hot-carrier stressed high-frequency noise model for metal–oxide–semiconductor field-effect transistors (MOSFETs). We first use the analytical method to develop a new fresh high-frequency noise model for MOSFETs, this model incorporates the effects of gate resistance, gate-induced current noise and non-local channel carrier heating, it can be used to calculate the minimum noise figure Fmin, optimized source admittance Yopt, and equivalent noise resistance Rn and admittance Gi. Secondly, we develop a new post-stress high-frequency noise model for MOSFETs, within this model the effects of hot-carrier stress induced interface states on the high-frequency noise performance can be evaluated. This model provides insightful device physics about the evolution of spatial noise sources within the channel versus stress time. The modeled results are in agreement with the experimental data of nMOSFETs with 0.25, 0.3 and 0.8-µm channel lengths.

Effects of hot carrier stress on the RF performance in SOI MOSFETs

This paper presents new experimental results on the DC hot carrier stress effects on the RF performance of SOI MOSFETs. The RF performance degradation in terms of cut-off frequency, minimum noise figure, and RF power has been measured and analyzed. The reduction of transconductance is turned out to be one of the major causes of the RF performance degradation. The measurement also shows that the RF performance degradation is more significant than the DC performance degradation. Especially, the degradation of minimum noise figure is the most significant.

Effects of hot-carrier stress on the performance of the lc-tank cmos oscillators

The effects of hot carrier stress on a fully integrated negative resistance LC-tank CMOS oscillator are investigated. The major effect is the decrease of the amplitude of the oscillation due to degradation in the I-V characteristics of the MOSFETs. The oscillator phase noise increases with stress duration since the amplitude of the oscillation decreases. A change in the biasing of the circuit due to the stress affects the parasitic capacitances in the circuit which in turn cause a slight change in the oscillation frequency.

About long-term effects of hot-carrier stress on n-MOSFETS

Transistor characteristics and charge-pumping results obtained during nonuniform long-term hot-carrier stress on n-MOSFETs (no LDD) will be presented. Apart from identifying the overall degradation processes and their drift dynamics, this work focuses on the dependence of the device damage on different stress conditions which are representative for typical applications in the large field of analogue and digital automotive electronic circuits.

Transconductance increase due to charge trapping during hot-carrier stress of nMOSFETs

An unusual hot-carrier degradation mode characterised by a transconductance increase during hot-carrier ageing of nMOS transistors is analysed. By measuring the effects of hot-carrier stress on drain and substrate characteristics and applying alternate static injection phases performed at different gate regimes, it is proved that the degradation is mainly due to negative charge trapping in a localised region near the drain. The transconductance increase is explained in terms of an exchange of the dominant role between the damaged and undamaged portions of the channel. This model is fully corroborated by 2D device electric simulation results.

Hot-carrier effects on the scattering parameters of lightly doped drain n-type metal-oxide-semiconductor field effect transistor

The latest evolution in complementary metal-oxide-semiconductor technology has made the metal-oxide-semiconductor field effect transistor (MOSFET) a viable choice for rf applications, especially for frequencies in the low GHz region. However, hot-carrier effects should also be considered carefully when the devices are operating in the GHz regime. Here, we studied the effects of dc hot-carrier stress on lightly doped drain (LDD) n-type MOSFET (NMOSFET) high-frequency performance by measuring and simulating its s parameters. This is the first time, to the authors’ best knowledge, that such experiments are reported. We demonstrated clearly the effects of hot-carrier stressing on LDD NMOSFETs by giving representative s-parameter and noise measurement results from a 0.8 μm long device. We showed that hot-carrier stress can significantly degrade both s parameters and noise of NMOSFETs, and thus can have considerable consequences for circuit designers. Therefore, these effects should be carefully considered when using MOSFETs in high-frequency analog circuits. Unfortunately, both MEDICI® and SPICE simulation could not satisfactorily model the LDD MOS structure after hot-carrier stress. Various results indicated that the current MEDICI platform is not very consistent for ac simulation, although dc simulation is very good. SPICE simulation showed very promising results when modeling the changes in S12 and S21 due to hot-carrier stress, yet the results for S11 and S22 were not very good. This deficiency implies that a better small-signal model for LDD MOS structures would be necessary for SPICE to be useful in modeling hot-carrier effects on MOSFET high-frequency performance.

Hot-carrier effects on the scattering parameters of lightly doped drain n-type metal–oxide–semiconductor field effect transistors

The latest evolution in complementary metal–oxide–semiconductor technology has made the metal–oxide–semiconductor field effect transistor (MOSFET) a viable choice for rf applications, especially for frequencies in the low GHz region. However, hot-carrier effects should also be considered carefully when the devices are operating in the GHz regime. Here, we studied the effects of dc hot-carrier stress on lightly doped drain (LDD) n-type MOSFET (NMOSFET) high frequency performance by measuring and simulating its s parameters. This is the first time, to the author’s best knowledge, that such experiments are reported. We demonstrated clearly the effects of hot-carrier stressing on LDD NMOSFETs by giving representative s parameter and noise measurement results from a 0.8 μm long device. We showed that hot-carrier stress can significantly degrade both s parameters and noise of NMOSFETs, and thus can have considerable consequences for circuit designers. Therefore, these effects should be carefully considered when using MOSFETs in high frequency analog circuits. Unfortunately, both MEDICI and SPICE simulation could not satisfactorily model the LDD MOS structure after hot-carrier stress. Various results indicated that the current MEDICI platform is not very consistent for ac simulation, although dc simulation is very good. SPICE simulation showed very promising results when modeling the changes in S12 and S21 due to hot-carrier stress, yet the results for S11 and S22 were not very good. This deficiency implies that a better small-signal model for LDD MOS structures would be necessary for SPICE to be useful in modeling hot-carrier effects on MOSFET high frequency performance.

Hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps ( Delta D/sub it/) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike Delta D/sub it/. Besides band-to-band (B-B) tunneling, Delta D/sub it/ introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A study of the increased effects of hot-carrier stress on NMOSFETs at low temperature

Summary form only given. It is well known that hot-carrier (HC) degradation of NMOSFETs is enhanced at low temperature (LT). Up to now, this has mainly been attributed to the greater mean free path of carriers at LT, which acquire more kinetic energy between two scattering events. It is shown that this is not the unique cause. It is demonstrated that the same density of HC generated defects modifies the electric characteristics of NMOSFETs at 77 K much more than it does at 300 K. There exist several possible explanations for the observed enhancement of degradation at LT: (1) the effect of Coulomb scattering by tapped charges on mobility degradation is relatively more important at LT; and (2) since at LT the Fermi level is closer to the conduction band in strong inversion, acceptor interface state levels near the conduction band are more populated with electrons. From simulations, it is concluded that (1) substantially enhances the effects of stress at LT, while (2) has no effect in weak inversion. Measurements show that the operating voltage of devices that work at 77 K should be reduced even when they are occasionally operating at 300 K. >

Analysis of MOSFET degradation due to hot-electron stress in terms of interface-state and fixed-charge generation

An analysis of MOSFET degradation induced by hot-electron stress is carried out by separating the effects of generated fixed-oxide charge ΔQ F, due to trapped electrons in the gate oxide and charge in the generated interface states ΔQ i. Both influences are considered in the subthreshold and above-threshold bias regions using a model for the stressed device which divides its channel into two regions having different threshold voltages. A phyiscal explanation is offered for degradation of transconductance g m by considering the V G dependence of the charge in the interface states ΔQ i and the threshold voltage V T. It is predicted that an increase in Q F alone causes the magnitude of the threshold voltage V T to increase and the device turn-on to become more abrupt (transconductance g m increases), while an increase in Q i alone results in a softer turn-on ( g m decreases) and makes the threshold voltage dependent on V G. The generated interface state density D it and the fixed charge density ΔQ F is extracted by fitting the measurements to the above threshold I D- V G characteristics (small drain voltages) calculated with the model. Furthermore, we find that while both Q F and Q i increase monotonically with stress, the contribution of ΔQ i to the change in V T is significantly larger than that due to the change in Q F. This conclusion is independent of stress time or of the exact division of the channel (the assumed lengths L 1 and L 2). Interface state densities obtained from the measured slopes of subthreshold I D- V G plots (which are affected by states near the middle of the band gap) are appreciably lower than densities deduced from measurements made above threshold (which are sensitive to states near the band edges) using the divided-channel representation. An increased dependence of subthreshold current on V D after stress is attributed to short-channel behavior of the MOSFET in the vicinity of the drain. The effects of hot-carrier stress in p-channel MOSFETS are also interpreted in terms of the two-transistor representation.