Effective Number Of Bits Research Articles

Calibration on timing skew mismatch in time-interleaved ADCs based on self-adaptive particle swarm algorithm

The timing skew mismatch is one of the limitations in the Time-interleaved Analog-to-Digital Converter (TIADC) system seriously degrades the system performance. In order to solve this problem, this paper proposes an algorithm to detect the timing skew mismatch. The self-adaptive Particle Swarm Optimization (SAPSO) algorithm was used to detect the timing skew mismatch in the TIADC system, and the variable delay line (VDL) was used to calibrate the detected timing skew mismatch. For verifying the effectiveness of the proposed algorithm, a 4-channel, 1 GHz and 18 bits TIADC system model with timing skew mismatch is established. The simulation results show that the proposed algorithm significantly improves the performance of the TIADC system, which the Spurious Free Dynamic Range (SFDR) is increased by 61.1 dB on average, the Signal-to-Noise Ratio (SNR) is increased by 59.17 dB on average, and the effective Number of Bits (ENOB) is increased by 9.83 bits on average. Compared with the previous calibration algorithms, the proposed method has the advantages of simple structure, fast detection speed and high accuracy.

The spectrometer development of CosmoCube, lunar orbiting satellite to detect 21-cm hydrogen signal from cosmic dark ages

Abstract The cosmic Dark Ages represent a pivotal epoch in the evolution of the Universe, marked by the emergence of the first cosmic structures under the influence of dark matter. The 21-cm hydrogen line, emanating from the hyperfine transition of neutral hydrogen, serves as a critical probe into this era. We describe the development and implementation of the spectrometer for CosmoCube, a novel lunar orbiting CubeSat designed to detect the redshifted 21-cm signal within the redshift range of 13 to 150. Our instrumentation utilizes a Xilinx Radio Frequency System-on-Chip (RFSoC), which integrates both Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), tailored for the spectrometer component of the radiometer. This system is characterized by a 4096 FFT length at 62.5 kHz steps using a Polyphase Filter Bank (PFB), achieving an average Effective Number of Bits (ENOB) of 11.5 bits throughout the frequency of interest, from 10 MHz to 100 MHz. The spectrometer design is further refined through loopback tests involving both DAC and ADC of the RFSoC, with DAC outputs varying between high (+1 dBm) and low (-3 dBm) power modes to characterize system performance. The power consumption was optimized to 5.45 W using three ADCs and one DAC for the radiometer. Additionally, the stability of the ADC noise floor was investigated in a thermal chamber with environmental temperatures ranging from 5○C to 40○C. A consistent noise floor of approximately -152.5 dBFS/Hz was measured, with a variation of ±0.2 dB, ensuring robust performance under varying thermal conditions.

All-optical digital-to-analog conversion based on pulse walk-off effect

A novel approach for all-optical digital-to-analog conversion (DAC) based on the pulse walk-off effect is proposed and experimentally demonstrated. In this approach, an ultrafast optical pulse train is firstly spectrum-tailored by a spectrum-shaper to achieve the multi-wavelength pulses, serving as the sampling source for carrying serial input digital signals via intensity modulation. These modulated optical signals are then injected into a dispersion medium to introduce multi-wave pulse walk-off. Consequently, the modulated optical signals partially overlap in the time domain and the incoherent weighted intensity summation can be realized. The following intensity modulator driven by the selecting codes extracts the target signals in the right time slots. The proposed approach features all-optical structure, inter-channel error avoidance, and high conversion rate, offering a promising solution for achieving high-performance photonic DAC. A proof-of-concept experiment of a 3-bit DAC system with a conversion rate of 5 Gbps based on the pulse walk-off effect has been successfully carried out. Additionally, the system’s performance in terms of Effective number of bits (ENOB) versus modulator extinction ratio and dispersion fluctuations is also discussed in detail.

In-Depth Analysis of Low-Cost Micro Electromechanical System (MEMS) Accelerometers in the Context of Low Frequencies and Vibration Amplitudes.

Shock and vibration hazards to civil structures are common and come not only from earthquakes but most often from mining operations or foundation work involving the installation of piles using hammer-driving and vibrating technology. The purpose of this study is to present test methods for low-cost MEMS accelerometers in terms of their selection for low-amplitude acceleration vibration-prone object-monitoring systems. Tests of 24 commercially available digital accelerometers were carried out on a custom-built test bench, selecting four models for detailed tests conducted on a specially built precision vibration table capable of inflicting accelerations at frequencies of 1-2 Hz, using displacements as small as a few micrometers. The analysis of the results was based, among other things, on a modified method of determining the signal-to-noise ratio (SNR) and also on the idea of the effective number of bits (ENOB). The results of the analysis showed that among low-cost MEMS accelerometers, there are some that are successfully suitable for the monitoring and warning of excessive vibration hazards in situations where objects are extremely sensitive to such impacts (e.g., treatment rooms in hospitals). Examples of accelerometers capable of detecting harmonic vibrations with amplitudes as small as 10 mm/s2 or impulsive shocks with amplitudes of at least 70 mm/s2 are indicated.

A Wireless Miniature Injectable Device with Memory-Assisted Backscatter for Multimodal Animal Physiological Monitoring.

This paper introduces a wirelessly powered multimodal animal physiological monitoring application-specific integrated circuit (ASIC). Fabricated in the 180 nm process, the ASIC can be integrated into an injectable device to monitor subcutaneous body temperature, electrocardiography (ECG), and photoplethysmography (PPG). To minimize the device size, the ASIC employs a miniature receiver (Rx) coil for wireless power receiving and data communication through a single inductive link operating at 13.56 MHz. We propose a folded L-shape Rx coil with improved coupling to the transmitter (Tx) coil, even in the presence of misalignment, and enhanced quality factor. The ASIC functions alternatively between recording and sleeping modes, consuming 2.55 μW on average. For PPG measurements, a reflection-type PPG sensor illuminates an LED with tunable current pulses. A current-input analog frontend (AFE) amplifies the current of a photodiode (PD) with 30.8 pARMS current input-referred noise (IRN). The ECG AFE captures ECG signals with a configurable gain of 45-80 dB. The temperature AFE achieves 0.02 ̊C inaccuracy within a sensing range between 27-47 ̊C. The AFE outputs are sequentially digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an effective number of bits (ENOB) of 8.79. To improve the reliability of data transmission, we propose a memory-assisted backscatter scheme that stores ADC data in an off-chip memory and transmits it when the coupling condition is stable. This scheme achieves a package loss rate (PLR) lower than 0.2% while allowing 24-hour data storage. The device's functionality has been evaluated by in vivo experiments.

Multi-channel photonic sampled ADC with hybrid deep-learning for distortion recovery

Analog-to-digital converter (ADC) is indispensable components in modern information systems, and photonic technologies have emerged as promising avenues for overcoming bottlenecks in ADC performance. This paper introduces a novel approach: a photonic sampled ADC integrated with a neural network that combines Convolutional Neural Networks (CNNs) and Transformers for data recovery. The proposed system utilizes a multi-wavelength optical sampling pulse train interleaved in the time domain through fiber dispersion. Sampled signals are quantified in parallel channels by electronic ADC (EADC). Through supervised training, the hybrid deep neural network extracts both local and global features of photonic system defects, enabling the recovery of distorted data. Experimental validation showcases the effectiveness of this architecture, achieving successful reconstruction of radio frequency (RF) signals at a sampling rate of 12 Giga-samples per second (Gs/s) with an effective number of bits (ENOB) of 7.13. The results underscore the potential of the proposed architecture in achieving high conversion accuracy in multi-channel photonic sampled ADCs.

Signal-to-noise ratio enhancement for digitalizing low amplitude wideband signals in photonic analog-to-digital converters.

Photonic analog-to-digital converters (PADCs) have been investigated for nearly five decades as a promising approach to overcome the bandwidth and jitter problem and bring ADC performance to new levels. However, low-amplitude signals often struggle to achieve full-scale quantization accuracy, posing a basic challenge for achieving high signal-to-noise ratio (SNR) digitization. Here, we established an optical carrier-to-sideband ratio (OCSR) based sampler model to achieve the optimal combination of the modulation, loss compensation, and photoelectric detection processes. The OCSR-based sampler features the advantages of high useful signal gain, low noise figure, and the ability to function over a very wide frequency range. The low-bias region is investigated, and the corresponding OCSR is selected as the transfer function for the Mach-Zehnder modulator (MZM). The OCSR-based sampler enables a higher gain of the radio frequency (RF) information signal sidebands. After the beating at the photodetector, the useful signal power reaches the digitizer's full scale to fully utilize the quantization accuracy, thereby enhancing the SNR of the whole system. In the experiment, a 20 GSa/s PADC with 4 interleaved sub-channels is configured out. Considerable advantages of the proposed OCSR-based sampler over conventional quadrature-biased sampler are demonstrated in comparative tests. A ∼5 dB enhancement in SNR and an increase of ∼0.8 effective number of bits (ENOB) are achieved under sinusoidal signals, and linear frequency modulation (LFM) signals with 8 GHz instantaneous bandwidth as well.

A Low-Power, High-Resolution Analog Front-End Circuit for Carbon-Based SWIR Photodetector

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems.

A heterogenous integrated neural recording system with elastocapillary self-assembled Au-PDMS-PEG neural probe and customized ASIC

Abstract This study presents the design and implementation of a heterogenous integrated neural recording system consisting of a flexible Au-PDMS-PEG probe and customized complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) in a standard 0.18 μm process. The flexible Au-PDMS-PEG probe was prepared by an elastocapillary self-assembled process, achieving an electrode impedance of 250 kΩ (@1 kHz). The customized CMOS ASIC contains 36 modular digital pixels (MDP). It achieves 5.69 μVrms input referred noise, 10.29 effective number of bits, 49.5 μW power consumption, and 0.092 mm2 area for a single MDP unit. Spontaneous spikes were also recorded in the mouse cortex, with a peak-to-peak amplitude of 389.2 μVPP and a signal-to-noise ratio of 19.36. Benchtop and in-vivo experiments were conducted to validate the functionality and performance of the proposed neural recording system.

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

SWITCHING RIPPLE DATA TRANSFER TECHNIQUE USING STEP-DOWN DC-DC CONVERTER

This paper describes an electronic communication method based on the use of the DC-DC converter as a data transfer device. Output voltage of a DC-DC converter is modulated with Amplitude-Shift Keying (ASK) signal carrier. Modulation takes place in the feedback loop of the DC-DC converter. The output signal passes through the transition line to the band pass filter, where unexpected noise and DC components are removed. Transition line is represented as a long wire with a certain length that contains active and reactive parasitic parameters. These parameters affect Total Harmonic Distortion (THD) of the initial ASK signal waveform. Switching ripple communications are introduced to simplify electrical connection and reduce the wire count. This makes it particularly suitable for Internet of Things (IoT) applications in challenging environments where RF may be weak or unreliable. Nowadays wiring is an expensive part of electronic products. Industry leading companies usually spend sufficient resources on wiring production and installation work. Switching ripple communication modules can reduce a final product price and increase reliability. Also, these systems can be easily implemented to existing designs because power line communication devices do not require additional signal pass conductors or additional RF modules for data transfer. The proposed communication method can be used in such industries as: battery management systems, industrial lightning control, automotive or even in high performance power supplies for telecom solutions. The purpose of this paper is to create a signal transfer model and show a dependency between transition wire length and total harmonic distortion parameter, which affects output signal. Low THD parameter is important for carrier signal decode operations. After the filtering stage ASK signal usually passes to the Microcontroller unit through the Analog to Digital converter (ADC) block. By increasing carrier signal THD the ADC effective number of bits (ENOB) parameter will be affected. As a result, all further signal processing stages such as digital filtering and calculations will take more hardware resources.

A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs.

Quantitative analysis of the high speed and high precision waveform digital system for Jinping Neutrino Experiment

The Jinping Neutrino Experiment (JNE) aims to construct a 500-ton liquid scintillator detector for detecting and studying neutrinos. In JNE data analysis, particle energy and position reconstruction are crucial, with result accuracy closely related to the performance of the waveform digitization system. This study developed a quantitative model to explore correlations between sampling characteristics (effective number of bits and sampling rate) and detector system performance (single photoelectron charge spectrum resolution and transfer time spread). Additionally, three ADCs (Tsinghua ADC13B1G, ADI AD9695, TI ADS54J60) and MCP-PMTs were utilized to validate the model accuracy. The experimental results for the system charge spectrum resolution are in alignment with the theoretical predictions. When the ENOB of the ADC exceeds 10.66-bit and the sampling rate exceeds 1 GSPS, the system charge spectrum resolution is better than 45%, approaching the PMT inherent resolution of 44%. The transfer time spread within the system demonstrates minimal impact from the ADC sampling characteristics. These results serve as a reference for upgrading the JNE 60-channel and 4000-channel readout electronic systems. Additionally, this study can assist developers in maximizing the performance of physics experiment readout electronics systems within constrained budgets.

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

Efficient Direct Detection of Twin Single-Sideband Quadrature-Phase Shift Keying Using a Single Detector with Hierarchical Blind-Phase Search

We propose a novel reception scheme for twin single-sideband (twin-SSB) signals using just a single photodetector (PD), significantly reducing the system complexity and cost. To detect a twin-SSB with power-unbalanced quadrature-phase shift keying (QPSK) sidebands upon detection via a single PD at the receiver side, two QPSKs carried in two sidebands are coherently superposed and detected in a 16-ary quadrature amplitude modulation (16-QAM) format. This technique notably diminishes the linearity and effective number of bits required for the transmitter components in high-speed optical transmission systems. Moreover, a hierarchical blind-phase search (HBPS) algorithm is proposed to compensate for the imperfect phase rotation of QPSK signals during transmission. To demonstrate the effectiveness of our proposed method, we successfully conducted simulations of 112 Gb/s 16-QAM signal transmission over a 10 km standard single-mode fiber (SSMF), achieving bit error ratios (BERs) of 7.84×10−4, well below the 7% hard-decision forward error correction (HD-FEC) threshold of 3.8×10−3. In addition, the synthetic transmission scheme proposed in this paper is compared with the traditional 16-QAM signal transmission scheme, and the results show that the proposed scheme does not introduce a performance cost with the same received optical power (ROP) and transmission distance.

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

A hybrid SAR ADC with input range extension

—This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR) analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor units and a reference voltage VREF, it attains a ±1.875VREF input range and a resolution of 10.91 bits. The hybrid SAR ADC decomposes the capacitive digital-to-analog converter (CDAC) into an incremental CDAC and a binary-weighted CDAC. For input signals larger than 0.75 VREF, the incremental CDAC is used to reduce the net sampling charge by biasing its capacitor bottom plates on proper reference voltage to implement input range extension. Furthermore, the increment CDAC contributes to enhancing linearity. The input frequency limitation is theoretically analyzed in the paper. This design is implemented with a 180-nm CMOS technology and achieves a 10.47 effective number of bits (ENOB). It consumes 26.8 μW at 1 MS/s with a 1.8-V supply and occupies an area of 0.0118 mm2.

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.