Effective Number Of Bits Research Articles

A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction.

This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.

High-resolution calibrated successive-approximation-register analog-to-digital converter

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively.

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components.

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

A 64-Channel Data Acquisition System-Based Ultralow Noise Transimpedance Amplifier for an Ionization Profile Monitor

To meet the high time-resolution requirements of a fast ionization profile monitor (IPM), a 64-channel electrical signal acquisition system with a fast response frequency of 1 MHz has been developed. This article initially describes an ultralow noise transimpedance amplifier, which is an analog front-end (AFE) electronics aiming to achieve a balance between the accuracy and bandwidth, as well as to truly reflect the microstructure of short beam pulses. Subsequently, a synchronized multichannel data transmission system based on field-programmable gate arrays (FPGAs) transmits data streaming with the low latency and high throughput, and meanwhile, it provides data homogeneity in time across channels. The system is designed in a modular way to easily extend up to 128 channels. The nonlinearity of the readout electronics is less than 0.2% in the dynamic range of 15 nA– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15~\mu \text{A}$ </tex-math></inline-formula> , and the relative resolution is 0.15% at the input current of 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> . The spurious-free dynamic range (SFDR) is about 82.43 dB at a fundamental frequency of 1 kHz, and the effective number of bits (ENOB) of the analog-to-digital conversion (ADC) is better than 13 bits. The relative synchronization time discrepancy between channels is better than 2.5% of the sampling cycle. Finally, the system is deployed for the beam profile measurement with an IPM. The obtained peak value shows a good proportionality with the beam intensity increment, and all the electronics properties achieve reasonable and excellent performance.

Photonic sampling analog-to-digital conversion based on time and wavelength interleaved ultra-short optical pulse train generated by using monolithic integrated LNOI intensity and phase modulator.

High-speed analog-to-digital conversion (ADC) is experimentally demonstrated by employing a time and wavelength interleaved ultra-short optical pulse train to achieve photonic sampling and using wavelength division demultiplexing to realize speed matching between the fast optical front-end and the slow electronic back-end. The sampling optical pulse train is generated from a cavity-less ultra-short optical pulse source involving a packaged device that monolithically integrates an intensity modulator and a phase modulator into a chip based on lithium niobate on insulator (LNOI). In the experiment, the fiber-to-fiber insertion loss of the packaged modulation device is measured to be 6.9 dB. In addition, the half-wave voltages of the Mach-Zehnder modulator and the phase modulator in the LNOI-based modulation device are measured to be 3.6 V and 3.4 V at 5 GHz, respectively. These parameters and the device size are superior to those based on cascaded commercial devices. Through using the packaged modulation device, two ultra-short optical pulse trains centered at 1541.40 nm and 1555.64 nm are generated with time jitters of 19.2 fs and 18.9 fs in the integral offset frequency range of 1 kHz to 10 MHz, respectively, and are perfectly time interleaved into a single pulse train with a repetition rate of 10 GHz and a time jitter of 19.8 fs. Based on the time and wavelength interleaved ultra-short optical pulse train, direct digitization of microwave signals within the frequency range of 1 GHz to 40 GHz is demonstrated by using a two-channel wavelength demultiplexing photonic ADC architecture, where the effective number of bits are 5.85 bits and 3.75 bits for the input signal at 1.1 GHz and 36.3 GHz, respectively.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure of merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.

An 8.25b-ENOB 100kSps 290fJ-FoM asynchronous SAR capacitance to digital converter

This paper presents a low-power asynchronous capacitance to digital converter achieving 8.25-bit Effective Number of Bits (ENOB), and 290-fJ/conversion.step Figure of Merit (FoM) at 100 kHz sampling per cycle and 1.4 V supply voltage. The asynchronous mechanism enables the converter to generate an internal clock signal itself and therefore reduces the design complexity and power-consumption. Moreover, a differential architecture relying on the sole capacitive sensor guarantees that performance of the converter is not affected by fluctuations of the input capacitance and of the comparator common-mode voltage during the conversion. A prototype being fabricated in standard 0.18 μm CMOS technology occupies 0.13 mm2 area, though, this can be reduced if capacitor arrays cancelling the initial capacitance of the sensor at the atmospheric pressure are alleviated. Measurement result fits with the real capacitive sensor characteristic.

The Effect of Bit Depth on High-Temperature Digital Image Correlation Measurements

Digital Image Correlation (DIC) is a camera-based method of measuring displacement and strain. High-temperature DIC is challenging due to light emitted from the sample which can saturate the image. This effect can be mitigated using optical bandpass filters, but the maximum sample temperature range of DIC remains dependent on the camera and camera settings. Among camera settings, bit depth, also referred to as color depth or number of bits, has received insufficient attention in high-temperature DIC literature. In this work, the effect of bit depth on DIC measurements is investigated both analytically and experimentally. It is shown that if image noise is sufficiently low, then increasing bit depth reduces DIC random error. A new metric, the effective number of bits, is presented to determine the appropriate number of bits for DIC images. Using increased bit depth, reduced exposure time, and low-noise images, the maximum sample temperature for DIC measurements was shown to increase without negatively impacting random error.

A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC

This article reports a fourth-order continuous-time (CT) delta&#x2013;sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain&#x2013;bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

Noise analysis of photonic digital-to-analog converters.

Photonic digital-to-analog converters (PDACs) have a broad application prospect due to the ability to overcome the non-idealities in electronic circuits. PDACs are usually implemented by quantizing and summing the optical intensities of multiple lasers. The relative intensity noise of laser sources plays a critical role in determining the signal-to-noise ratio (SNR) and effective number of bits (ENOB). We present a detailed noise analysis for PDACs. Both the traditional binary-weighted structure and the recently proposed segmented-weighted structure are investigated. The results show that laser noise imposes a fundamental limit to the maximum SNR and ENOB that can be achieved in binary-weighted PDACs, while segmented PDACs can break this limitation and have a continuously increasing SNR with the quantization bit number (QBN). A novel configuration based on laser multiplexing and balanced detection, to the best of our knowledge, is also proposed and analyzed to increase the number of bits when the number of lasers is limited. Numerical simulations are performed to evaluate the SNR evolution with the QBN in different types of PDACs. The results are in good agreement with the theoretical analysis. Our analysis provides useful insights and can be important guidance for implementing high-performance PDACs.

Photonic-aware neural networks

Photonics-based neural networks promise to outperform electronic counterparts, accelerating neural network computations while reducing power consumption and footprint. However, these solutions suffer from physical layer constraints arising from the underlying analog photonic hardware, impacting the resolution of computations (in terms of effective number of bits), requiring the use of positive-valued inputs, and imposing limitations in the fan-in and in the size of convolutional kernels. To abstract these constraints, in this paper we introduce the concept of Photonic-Aware Neural Network (PANN) architectures, i.e., deep neural network models aware of the photonic hardware constraints. Then, we devise PANN training schemes resorting to quantization strategies aimed to obtain the required neural network parameters in the fixed-point domain, compliant with the limited resolution of the underlying hardware. We finally carry out extensive simulations exploiting PANNs in image classification tasks on well-known datasets (MNIST, Fashion-MNIST, and Cifar-10) with varying bitwidths (i.e., 2, 4, and 6 bits). We consider two kernel sizes and two pooling schemes for each PANN model, exploiting 2times 2 and 3times 3 convolutional kernels, and max and average pooling, the latter more amenable to an optical implementation. 3times 3 kernels perform better than 2times 2 counterparts, while max and average pooling provide comparable results, with the latter performing better on MNIST and Cifar-10. The accuracy degradation due to the photonic hardware constraints is quite limited, especially on MNIST and Fashion-MNIST, demonstrating the feasibility of PANN approaches on computer vision tasks.

A Low-Noise and Monolithic Array Tactile Sensor Based on Incremental Delta-Sigma Analog-to-Digital Converters

A low-noise and monolithic array tactile sensor, in which a tactile sensing unit, a low-noise analog front end (AFE), and a high-resolution delta-sigma analog-to-digital converter (ΔΣ ADC) are fully integrated, is presented in this paper. In this proposed system, compared with a discrete-device-based board-level system, the parasitic effect of a long cable connection can be reduced, and results are more accurate. Furthermore, a smaller system area and a lower power consumption can be achieved in this monolithic system. A discrete-continuous mixed mode bandpass AFE is proposed to filter out low-frequency flicker noise and high-frequency white noise. In order to improve the quantization rate of the sensor readout circuit and further suppress the high-frequency noise, a two-way alternate sample-and-hold circuit scheme is adopted in this design. The proposed tactile sensor is designed and fabricated in a 0.5-μm CMOS (Complementary metal oxide semiconductor)mixed-signal process with a 16 × 16 array and a total chip area of 1.9 × 1.9 cm2. This chip consumes 33.5 mW from a 5 V supply. The measurement results showed that the signal-to-noise and distortion rate (SNDR) was 65.2894 dB and that the effective number of bits (ENoB) was 10.553 dB. Moreover, this sensor could achieve a pressure measurement range of 0.002–0.5 N with a resolution of 0.4 mN.

A four-channel coincidence digital positron annihilation lifetime spectrometer

Positron annihilation lifetime (PAL) spectrometer is an effective tool to investigate material microstructures. Commonly used PAL spectrometers are conventional PAL spectrometer based on nuclear instrument modules (NIMs) and digital PAL spectrometer based on ultra-high-speed digitizer. Limited by the detection efficiency of the detectors, the coincidence count rate of the PAL spectrometer is always low, causing long time consumption of measurement. To solve this problem, a multi-channel coincidence method based on the ultra-high-speed digitizer was proposed. However, the ultra-high-speed digitizer is usually excessively expensive for research institutes. In this paper, we introduce a four-channel coincidence digital PAL spectrometer. Through the improvement of the timing and trigger circuit, all channels can act as start and stop channels during one measurement. Hence the coincidence count rate can be increased by an order of magnitude. The time measurement shows good linearity and high resolution with a full width half maximum (FWHM) at a level of several tens picoseconds. The effective number of bits (ENOB) of the analog-to-digital converter (ADC) reaches 10.72 bits. The energy resolution of the 511 keV photopeak reaches 4.16% when using LaBr 3: 5% Ce3+ scintillator, better than 4.62% of the conventional spectrometer. The time resolution of our PAL spectra when one channel receives start signals and one channel receives stop signals reaches 193.7 ps, better than that of the conventional spectrometer (212.8 ps). The FWHMs of the lifetime spectra of the two and four channel coincidence measurements are 205.8 ps and 212.4 ps respectively. Moreover, the coincidence count rate of our system increases significantly by using the four-channel coincidence method, which can be 10 times higher than the conventional spectrometer.

High-Bandwidth Arbitrary Signal Detection Using Low-Speed Electronics

The growing demand for bandwidth and energy efficiency requires new solutions for signal detection and processing. We demonstrate a concept for high-bandwidth signal detection with low-speed photodetectors and electronics. The method is based on the parallel optical sampling of a high-bandwidth signal with sinc-pulse sequences provided by a Mach-Zehnder modulator. For the electronic detection and processing this parallel sampling enables to divide the high-bandwidth optical signal with the bandwidth <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$B$</tex-math></inline-formula> into <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N$</tex-math></inline-formula> electrical signals with the baseband bandwidth of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$B/(\text{2}\,N)$</tex-math></inline-formula> . In proof-of-concept experiments with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N=3$</tex-math></inline-formula> , we present the detection of 24 GHz optical signals by detectors with a bandwidth of only 4 GHz. For ideal components, the sampling and bandwidth down-conversion does not add an excess error to the signals and even for the non-ideal components of our proof-of-concept setup, it is below 1%. Thus, the rms error for the measurement of the 24 GHz signal was reduced by a factor of about 3.4 and the effective number of bits were increased by 1.8.

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

Joint Error Estimation and Calibration Method of Memory Nonlinear Mismatch for a Four-Channel 16-Bit TIADC System.

Memory nonlinear error greatly reduces the performance of analog-to-digital converters (ADCs), and this effect is more serious in a time-interleaved analog-to-digital converter (TIADC) system. In this study, the sinusoidal wave fitting method was adopted and a joint error estimation method was proposed to address the memory nonlinear mismatch problem of the current TIADC system. This method divides the nonlinear error estimation method into two steps: the nonlinear mismatch error is coarsely estimated offline using the least squares (LS) method, and then accurately estimated online using the recursive least squares (RLS) method. After the estimation, digital post-compensation method is adopted. The obtained error parameters are used to reconstruct the error and then the reconstructed error is reduced at the output. This study used a four-channel 16-bit TIADC system with an effective number of bits (ENOB) value of 10.06 bits after the introduction of a memory nonlinearity error, which was increased to 15.42 bits after calibration by the joint error estimation method. As a result, the spurious-free dynamic range (SFDR) increased by 36.22 dB. This error estimation method can improve the error estimation accuracy and reduce the hardware complexity of implementing the error estimation system using a field programmable gate array (FPGA).

A novel noncoupling capacitor split capacitor array structure for high resolution SAR ADC

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11 [Formula: see text]m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC.

A 12-bit, 1.1-GS/s, Low-Power Flash ADC

In this article, an efficient architecture for a low-power, high-resolution flash analog-to-digital converter (flash ADC) is presented. It operates at 12-bit resolution with a sampling frequency of 1.1 GS/s. The architecture is a segmented one consisting of three subflash ADCs that we call SADC1, SADC2, and SADC3. During the operation, SADC1 detects the MSB bit, and SADC2 detects the intermediate bits, while SADC3 detects the finer bits of the flash ADC. Furthermore, SADC1 has a 1-bit resolution, SADC2 has a 6-bit resolution, and SADC3 has a 5-bit resolution. The binary operation related to 12-bit resolution is achieved by combining the subflash ADCs, thermometer digital outputs, and an encoder. The ADC has been fabricated in Global Foundry (GF) 65-nm standard CMOS process. The measured performance parameters show a differential nonlinearity (DNL) of &#x00B1;0.24 LSB, an integral nonlinearity (INL) of &#x00B1;0.45 LSB, a signal-to-noise and distortion ratio (SNDR) of 64.55 dB, a spurious-free dynamic range (SFDR) of 73.9 dB, and an effective number of bits (ENOB) of 10.43 bits. Also, power consumption is found to be 15.10 mW at 1.1-GS/s sampling frequency and 1.2-V supply voltage. The ADC achieves an FOM of 9.95 fJ/conversion-step (c-s) at the Nyquist input frequency and occupies a core area of 0.084 mm².

A Low Power Fully Differential Level-Crossing ADC With Low Power Charge Redistribution Input for Biomedical Applications

A low-power fully differential level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Different from conventional ADCs based on the uniform sampling rate, LC-ADC generates fewer samples for biomedical signals and leads to less power consumption in the following blocks. In this design, the power consumption of n-bit DAC and digital parts is reduced significantly with respect to the conventional LC-ADCs. The proposed method uses a charge redistribution block (CRB) instead of the n-bit DAC, which leads to a large reduction in average switching energy. Besides energy-saving, the proposed switching scheme also reduces the complexity of the controlling logic circuit, providing reduced complexity and low power consumption. Another advantage of the proposed LC-ADC is its fully differential structure. As a result, SNDR is improved by decreasing the levels of even harmonics. The proposed LC-ADC is designed in 0.18 um CMOS technology. Post-layout simulation results show an effective number of bits (ENOB) of up to 6.8 bits with about 97-188 nW power consumption under 0.8 V supply voltage and input signal bandwidth from 1 Hz to 4 kHz. The ADC occupies a silicon area of only 60×65 μm2.