Effective Number Of Bits Research Articles

In-Depth Analysis of Low-Cost Micro Electromechanical System (MEMS) Accelerometers in the Context of Low Frequencies and Vibration Amplitudes.

Shock and vibration hazards to civil structures are common and come not only from earthquakes but most often from mining operations or foundation work involving the installation of piles using hammer-driving and vibrating technology. The purpose of this study is to present test methods for low-cost MEMS accelerometers in terms of their selection for low-amplitude acceleration vibration-prone object-monitoring systems. Tests of 24 commercially available digital accelerometers were carried out on a custom-built test bench, selecting four models for detailed tests conducted on a specially built precision vibration table capable of inflicting accelerations at frequencies of 1-2 Hz, using displacements as small as a few micrometers. The analysis of the results was based, among other things, on a modified method of determining the signal-to-noise ratio (SNR) and also on the idea of the effective number of bits (ENOB). The results of the analysis showed that among low-cost MEMS accelerometers, there are some that are successfully suitable for the monitoring and warning of excessive vibration hazards in situations where objects are extremely sensitive to such impacts (e.g., treatment rooms in hospitals). Examples of accelerometers capable of detecting harmonic vibrations with amplitudes as small as 10 mm/s2 or impulsive shocks with amplitudes of at least 70 mm/s2 are indicated.

A Wireless Miniature Injectable Device with Memory-Assisted Backscatter for Multimodal Animal Physiological Monitoring.

This paper introduces a wirelessly powered multimodal animal physiological monitoring application-specific integrated circuit (ASIC). Fabricated in the 180 nm process, the ASIC can be integrated into an injectable device to monitor subcutaneous body temperature, electrocardiography (ECG), and photoplethysmography (PPG). To minimize the device size, the ASIC employs a miniature receiver (Rx) coil for wireless power receiving and data communication through a single inductive link operating at 13.56 MHz. We propose a folded L-shape Rx coil with improved coupling to the transmitter (Tx) coil, even in the presence of misalignment, and enhanced quality factor. The ASIC functions alternatively between recording and sleeping modes, consuming 2.55 μW on average. For PPG measurements, a reflection-type PPG sensor illuminates an LED with tunable current pulses. A current-input analog frontend (AFE) amplifies the current of a photodiode (PD) with 30.8 pARMS current input-referred noise (IRN). The ECG AFE captures ECG signals with a configurable gain of 45-80 dB. The temperature AFE achieves 0.02 ̊C inaccuracy within a sensing range between 27-47 ̊C. The AFE outputs are sequentially digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an effective number of bits (ENOB) of 8.79. To improve the reliability of data transmission, we propose a memory-assisted backscatter scheme that stores ADC data in an off-chip memory and transmits it when the coupling condition is stable. This scheme achieves a package loss rate (PLR) lower than 0.2% while allowing 24-hour data storage. The device's functionality has been evaluated by in vivo experiments.

Multi-channel photonic sampled ADC with hybrid deep-learning for distortion recovery

Analog-to-digital converter (ADC) is indispensable components in modern information systems, and photonic technologies have emerged as promising avenues for overcoming bottlenecks in ADC performance. This paper introduces a novel approach: a photonic sampled ADC integrated with a neural network that combines Convolutional Neural Networks (CNNs) and Transformers for data recovery. The proposed system utilizes a multi-wavelength optical sampling pulse train interleaved in the time domain through fiber dispersion. Sampled signals are quantified in parallel channels by electronic ADC (EADC). Through supervised training, the hybrid deep neural network extracts both local and global features of photonic system defects, enabling the recovery of distorted data. Experimental validation showcases the effectiveness of this architecture, achieving successful reconstruction of radio frequency (RF) signals at a sampling rate of 12 Giga-samples per second (Gs/s) with an effective number of bits (ENOB) of 7.13. The results underscore the potential of the proposed architecture in achieving high conversion accuracy in multi-channel photonic sampled ADCs.

A Low-Power, High-Resolution Analog Front-End Circuit for Carbon-Based SWIR Photodetector

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems.

A heterogenous integrated neural recording system with elastocapillary self-assembled Au-PDMS-PEG neural probe and customized ASIC

Abstract This study presents the design and implementation of a heterogenous integrated neural recording system consisting of a flexible Au-PDMS-PEG probe and customized complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) in a standard 0.18 μm process. The flexible Au-PDMS-PEG probe was prepared by an elastocapillary self-assembled process, achieving an electrode impedance of 250 kΩ (@1 kHz). The customized CMOS ASIC contains 36 modular digital pixels (MDP). It achieves 5.69 μVrms input referred noise, 10.29 effective number of bits, 49.5 μW power consumption, and 0.092 mm2 area for a single MDP unit. Spontaneous spikes were also recorded in the mouse cortex, with a peak-to-peak amplitude of 389.2 μVPP and a signal-to-noise ratio of 19.36. Benchtop and in-vivo experiments were conducted to validate the functionality and performance of the proposed neural recording system.

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs.

Quantitative analysis of the high speed and high precision waveform digital system for Jinping Neutrino Experiment

The Jinping Neutrino Experiment (JNE) aims to construct a 500-ton liquid scintillator detector for detecting and studying neutrinos. In JNE data analysis, particle energy and position reconstruction are crucial, with result accuracy closely related to the performance of the waveform digitization system. This study developed a quantitative model to explore correlations between sampling characteristics (effective number of bits and sampling rate) and detector system performance (single photoelectron charge spectrum resolution and transfer time spread). Additionally, three ADCs (Tsinghua ADC13B1G, ADI AD9695, TI ADS54J60) and MCP-PMTs were utilized to validate the model accuracy. The experimental results for the system charge spectrum resolution are in alignment with the theoretical predictions. When the ENOB of the ADC exceeds 10.66-bit and the sampling rate exceeds 1 GSPS, the system charge spectrum resolution is better than 45%, approaching the PMT inherent resolution of 44%. The transfer time spread within the system demonstrates minimal impact from the ADC sampling characteristics. These results serve as a reference for upgrading the JNE 60-channel and 4000-channel readout electronic systems. Additionally, this study can assist developers in maximizing the performance of physics experiment readout electronics systems within constrained budgets.

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.

Efficient Direct Detection of Twin Single-Sideband Quadrature-Phase Shift Keying Using a Single Detector with Hierarchical Blind-Phase Search

We propose a novel reception scheme for twin single-sideband (twin-SSB) signals using just a single photodetector (PD), significantly reducing the system complexity and cost. To detect a twin-SSB with power-unbalanced quadrature-phase shift keying (QPSK) sidebands upon detection via a single PD at the receiver side, two QPSKs carried in two sidebands are coherently superposed and detected in a 16-ary quadrature amplitude modulation (16-QAM) format. This technique notably diminishes the linearity and effective number of bits required for the transmitter components in high-speed optical transmission systems. Moreover, a hierarchical blind-phase search (HBPS) algorithm is proposed to compensate for the imperfect phase rotation of QPSK signals during transmission. To demonstrate the effectiveness of our proposed method, we successfully conducted simulations of 112 Gb/s 16-QAM signal transmission over a 10 km standard single-mode fiber (SSMF), achieving bit error ratios (BERs) of 7.84×10−4, well below the 7% hard-decision forward error correction (HD-FEC) threshold of 3.8×10−3. In addition, the synthetic transmission scheme proposed in this paper is compared with the traditional 16-QAM signal transmission scheme, and the results show that the proposed scheme does not introduce a performance cost with the same received optical power (ROP) and transmission distance.

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

A hybrid SAR ADC with input range extension

—This paper proposes a differential 10-bit 1 MS/s successive approximation register (SAR) analog to digital converter (ADC) with input range (IR) extension. Employing 512 capacitor units and a reference voltage VREF, it attains a ±1.875VREF input range and a resolution of 10.91 bits. The hybrid SAR ADC decomposes the capacitive digital-to-analog converter (CDAC) into an incremental CDAC and a binary-weighted CDAC. For input signals larger than 0.75 VREF, the incremental CDAC is used to reduce the net sampling charge by biasing its capacitor bottom plates on proper reference voltage to implement input range extension. Furthermore, the increment CDAC contributes to enhancing linearity. The input frequency limitation is theoretically analyzed in the paper. This design is implemented with a 180-nm CMOS technology and achieves a 10.47 effective number of bits (ENOB). It consumes 26.8 μW at 1 MS/s with a 1.8-V supply and occupies an area of 0.0118 mm2.

A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step.

A neural network‐based error correction in the first‐stage residue of pipelined analog to digital converters

SummaryAn analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

A CMOS 12-Bit 3MS/s Rad-Hard Digital-to-Analog Converter Based on a High-Linearity Resistor String Poly-Matrix

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor.

To reduce the power consumption of a TDC in high-speed applications, a TDC architecture applied to SS ADC is proposed to reduce redundant counting. This structure can remove the identical part between two rows of pixel signals in a CMOS image sensor by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. This structure requires the simultaneous readout of two rows of pixels in the high-speed CMOS image sensor. In the 110 nm CMOS process, simulation results show that the designed 5-bit TDC achieves an effective number of bits (ENOB) at 4.72 bits and a figure-of-merit (FOM) at 104.7-162.3 fJ/step, with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis

This study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18[Formula: see text][Formula: see text]m CMOS process. For a 51.514[Formula: see text]kHz sinusoidal 1[Formula: see text]V peak-to-peak differential input signal with a 1[Formula: see text]MSPs clock speed, the proposed circuit achieves 2.0141[Formula: see text]mV maximum sampling window error, 0.131[Formula: see text][Formula: see text]W power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.